Senior Engineer -Low Power CLP

Arm Limited; India; Hybrid; INR 2,500,000 - 4,000,000; Full time

Job summary

Arm Limited in India’s Solutions Engineering group seeks a seasoned verification engineer to drive RTL-to-Gate and Gate-to-GDS signoffs with a focus on low-power correctness. You will collaborate with design, verification, and implementation teams to validate power intent and resolve complex signoff issues for SoC/IP designs.

The role emphasizes hands-on use of CLP/VCLP, LEC, and UPF/CPF, plus scripting in TCL/Perl/Python to automate flows and improve productivity.

Qualifications

• 5+ years of relevant experience in logical signoff and low-power structural verification.
• Hands-on knowledge of UPF/CPF and SystemVerilog.
• Experience with CLP or VCLP tools for low-power verification.
• Experience with LEC and power-aware LEC; strong analysis and debugging skills.
• Ability to debug CLP/VCLP and LEC issues and drive closure.

Responsibilities

• Perform low-power verification using CLP or VCLP across RTL, netlist, and physical design.
• Verify and validate UPF implementations; resolve power-aware issues.
• Develop and maintain LEC flows and signoff methodologies.
• Drive signoff reports and closure for SoC/IP designs.
• Develop TCL, Perl, and Python scripts to automate verification tasks.

Skills

Low-power verification

SystemVerilog

UPF/CPF

LEC / Formality

TCL / Perl / Python

Tools

Cadence Conformal Low Power

Synopsys VCLP

Cadence Conformal LEC

Job description

Job Description: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If your interested in working with a team of collaborative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout

Responsibilities:

Low Power structural check

• Perform low-power verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP.
• Verify and validate UPF implementation across RTL, netlist, and physical design stages.
• Perform power-aware equivalence checking and resolve identified issues.
• Analyze, debug, and resolve CLP structural, rule-based, and power-aware verification failures.
• Implement SoC-level low-power structural checks and debug issues through closure.

Logical Equivalence Checking (LEC/Formality):

• Perform RTL-to-Synthesis, Synthesis-to-P&R, and ECO logic equivalence verification using Cadence Conformal LEC.
• Analyze, debug, and resolve non-equivalences and aborts across different stages of the design flow.
• Develop, automate, and maintain robust LEC flows and signoff methodologies.
• Drive LEC failure resolution and closure, and generate comprehensive signoff reports.
• Implement and debug SoC-level flat LEC runs through signoff.

Methodology and Automation:

• Develop TCL, Perl, and Python scripts to automate verification tasks and improve productivity.
• Build and maintain reusable verification flows and debug utilities to improve efficiency and scalability.
• Drive methodology enhancements for low-power verification signoff and efficient resolution of verification aborts.

Required Skills and Experience :

• We are looking for a candidate with 5+ years of relevant experience in logical signoff and low-power structural verification for sophisticated SoC and IP development programs.
• Strong experience with low-power design and verification, including hands-on knowledge of UPF/CPF and SystemVerilog.
• Hands-on experience with low-power verification tools such as Cadence Conformal Low Power (CLP) or Synopsys VCLP.
• Experience with Logic Equivalence Checking (LEC) and power-aware LEC, with strong skills in analyzing and resolving verification failures.
• Ability to effectively debug CLP/VCLP and LEC issues and drive them through closure.
• Understanding of synthesis and Place & Route (P&R) flows is an advantage.
• Ability to collaborate across design, verification, and implementation teams to support successful signoff of complex SoC and IP designs.

#LI-BB1

Accommodations at Arm

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Hybrid Working at Arm

Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don't discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.