Senior DFT Engineer

Synopsys Inc; Bengaluru; On-site; INR 900,000 - 1,200,000; Full time

Benefits offered by this job

Health and wellness benefits

Financial benefits

Comprehensive rewards

Professional development opportunities

Job summary

Synopsys Inc in Bengaluru is looking for an experienced engineer to drive innovations in Design for Test (DFT) tools that enhance chip development. You will develop test plans, automate test cases, and improve tool reliability for high-performance silicon used in AI and mobile applications.

This role requires a strong background in DFT technologies, RTL coding, and collaboration across teams. The company offers a comprehensive benefits package, emphasizing wellness and work-life balance.

Qualifications

• 3+ years of relevant experience in DFT or ASIC test.
• Hands-on expertise in JTAG, MBIST, and related architectures.
• Solid understanding of ASIC design flow.

Responsibilities

• Develop detailed test plans for new DFT features.
• Review specifications and provide feedback before product release.
• Collaborate to create in-house test cases and implement DFT solutions.
• Perform Quality of Results analysis and troubleshooting.
• Conduct diagnostics and debugging to improve tool reliability.

Skills

DFT technologies

RTL coding

Scripting in Python

Diagnostics analysis

Education

Bachelor's, Master's, or MTech in Electrical/Electronics Engineering, Computer Science, or related field

Tools

Verilog

System Verilog

VHDL

Perforce

Job description

We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are You have spent the last few years deep in the world of Design for Test, and you know that a good DFT flow is not just about coverage numbers, it is about catching the failure that would have cost millions in a production run. You think in test patterns, fault models, and compression ratios, and you have learned that the difference between a tool that works in theory and one that works in production is usually in the details someone missed three reviews ago. You are comfortable jumping between RTL debugging, Python automation, and customer architecture conversations without losing sight of what you are actually building. When a scan compression flow fails at 2am, you do not panic, you pull logs, trace the issue, and find the root cause. You ask the right questions when a spec is vague, and you push back when a test plan does not cover the corner cases that matter. You like hard problems, especially the ones where the answer is not obvious and requires you to think across multiple layers of the ASIC flow. You have worked with MBIST, ATPG, scan chains, and diagnostics enough to know where things break and how to fix them before they reach a customer.

At Synopsys, you will work on DFT tools that power silicon development. The team is global, the problems are real, and what you build will matter.

What You'll Be Doing

• Develop detailed test plans for new DFT features, then build, execute, and automate test cases using Verilog, System Verilog, or VHDL
• Review specifications and test plans from Product Engineering and R&D teams, providing feedback to ensure feature completeness before product release
• Collaborate with cross‑functional teams to create in‑house test cases and implement scalable DFT solutions tailored to customer architectures and methodologies
• Build and validate prototype test flows and reference designs that demonstrate new DFT features like compression, ATPG for transition delay faults, cell‑aware faults, and Memory and Logic BIST
• Perform Quality of Results analysis, troubleshooting, and root cause analysis to resolve complex issues across the ASIC flow, from synthesis to sign‑off
• Conduct diagnostics analysis and debugging to improve tool reliability, performance, and customer experience
• Work with AI agents to review and create assistive or generative AI documentation for test products, and manage performance and installation testing

The Impact You Will Have

• Improve the quality and performance of Synopsys DFT tools that customers rely on to ship high-performance silicon for AI, automotive, and mobile applications
• Enable customers to implement robust test methodologies that catch defects earlier, reduce silicon respins, and accelerate time to market
• Drive innovation in DFT automation and AI‑driven testing, making cutting‑edge solutions accessible across diverse industry segments
• Strengthen Synopsys reputation as a trusted partner in delivering scalable, reliable, and high‑performance test solutions
• Facilitate cross‑team knowledge sharing by providing actionable feedback and creating comprehensive documentation that helps engineers and customers alike
• Advance the adoption of new DFT features and methodologies, ensuring Synopsys products remain competitive and future‑ready
• Support the seamless integration of new test technologies, keeping Synopsys at the forefront of semiconductor innovation

What You'll Need

• Bachelor's, Master's, or MTech in Electrical/Electronics Engineering, Computer Science, or a related field with 3+ years of relevant experience in DFT or ASIC test
• Hands‑on expertise in DFT technologies such as JTAG, MBIST, Scan, ATPG, and related test architectures
• Proficiency in RTL coding using Verilog, System Verilog, and/or VHDL
• Advanced scripting skills in Perl, Tcl/Tk, Python, or similar languages for automation and tool integration
• Solid understanding of ASIC design flow, including design planning, synthesis, physical design, and sign‑off verification tools
• Familiarity with change management tools like Perforce for collaborative development and version control is a plus
• Experience with DFT compression, diagnostics, or AI‑enabled test automation is a plus

Who You Are

• You can debug a failing scan chain at 10pm, trace it back to a clock gating issue, and explain the root cause to an R&D engineer in two sentences without losing nuance
• You are organized enough to manage multiple test plans, automation scripts, and customer escalations at once, and disciplined enough to document what you learn along the way
• You do not wait for perfect information to get started, you work with what you have, ask the right questions, and move forward
• You push back when a test plan does not cover the corner cases that matter, and you advocate for quality even when timelines are tight
• You are comfortable working across global teams, bridging gaps between Product Engineering, R&D, and customer‑facing teams with clear communication and technical depth
• You enjoy learning new technologies and methodologies, whether it is a new fault model, a new scripting framework, or an AI‑driven test agent

The Team You'll Be Part Of

You will join the Synopsys Product Engineering Team within the Test Group, a dynamic organization focused on validating, hardening, and delivering cutting‑edge Design for Test solutions. The team is composed of engineers and innovators who collaborate across product engineering and R&D to create industry‑leading methodologies and tools. As part of Product Engineering, you will work at the intersection of customer requirements, product quality, and technical innovation, ensuring that DFT features are thoroughly tested, well‑documented, and ready for real‑world deployment. Together, you will address challenges in diverse domains such as autonomous systems, AI, high‑performance computing, and mobile networking, driving the next wave of silicon innovation.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.