Senior Design Engineer (Physical IP)

Arm; Bengaluru; Hybrid; INR 2,800,000 - 4,200,000; Full time

Job summary

Arm is seeking an experienced layout engineer in Bengaluru to develop custom standard cells for next-generation sub-3nm nodes. You will collaborate with circuit designers to deliver high-performance, area-efficient layouts and ensure clean verification through DRC/LVS and QA flows.

The role requires 3+ years in custom layout, proficiency in Cadence Virtuoso, and scripting for automation. Hybrid work setup and collaboration across PDk, design, and QA teams are expected.

Qualifications

• 3+ years of custom layout experience in logic standard cell development.
• Experience in 5nm, 3nm, or 2nm nodes with FinFET/GAA-based technologies.
• Proficiency in CADENCE Virtuoso and layout verification tools (DRC/LVS).
• Strong scripting skills: Python, PERL, SKILL, TCL.

Responsibilities

• Layout design of logic standard cells (inverters, muxes, flops) optimized for performance, area, and power.
• Collaborate with circuit designers to translate schematics into clean, compact layouts and support library validation flows.
• Drive DRC/LVS closure and layout QA using industry-standard tools and automation scripts.
• Automate layout QA, regression checks, and PDK-driven verifications; document changes and verification results.

Skills

Custom layout design

Automation scripting

Pin accessibility

PPA optimization

Tools

Cadence Virtuoso

DRC/LVS tools

SKILL/TCL scripting

Job description

Role Summary

Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on innovative technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.

Role Summary

Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on innovative technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.

In this role, you will be responsible for the layout development of Arm custom standard cells in the latest, sub-3nm process technology nodes. The ideal candidate will be an expert in standard cell layout, physical verification, and automation techniques. You will work in close collaboration with the circuit design team to provide optimally tuned layout, and validate them through QA flows that use a variety of tools. This role is crucial in delivering high-performance, area-optimized, and DRC-clean logic libraries for next-generation SoCs and custom digital IPs.

Key Responsibilities

• Layout design of logic standard cells (inverters, muxes, flops cells, complex logic gates) optimized for performance, area, and power.
• Work with automation and QA teams to support library validation flows.
• Collaborate with circuit designers to understand schematics and translate them into clean, compact layouts.
• Drive design rule clean (DRC) and layout vs. schematic (LVS) closure using industry-standard verification tools (e.g., Calibre ).
• Perform layout debugging and root-cause analysis for DRC, LVS, and other physical sign-off issues.
• Handle cell abutment, cell profiling, and cell integration constraints for logic libraries.
• Address layout-dependent effects (LDE) and double patterning/EUV compliance in advanced nodes.
• Review and debug standard cell physical views (LEF, GDS, abstract views) for integration into digital flows.
• Automate layout QA, regression checks, and PDK-driven layout verifications using scripts (e.g., SKILL, Python).
• Participate in library quality audits and delivery cycles including signoff package creation and documentation.

Required Skills And Experience

• 3+ years of custom layout experience in logic standard cell development.
• Proven track record of working at 5nm, 3nm, or 2nm nodes with FinFET/GAA-based technologies.
• Proficiency in Cadence Virtuoso.
• Deep understanding of advanced DRC rules, LVS methodologies, and multi-patterning constraints.
• Solid experience in cell layout optimization for PPA (Power, Performance, Area).
• Strong grip on pin accessibility, cell architecture trade-offs, and physical synthesis-aware design.
• Automate layout-related tasks and workflows using scripting languages like Python, PERL, SKILL, and TCL.
• Maintain accurate documentation of layout designs, changes, and verification results.
• Working knowledge of version control, configuration management, and flow automation
• Make effective use of AI tools and automation to improve productivity, accelerate learning, and enhance the quality of technical solutions
• Strong documentation and communication skills to interface with cross-functional teams (PDK, design, QA).
• Stay updated on best practices for standard cell layout, design rules, and advanced node requirements.

Nice To Have Skills And Experience

• Exposure to physical design implementation flow

Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.