Senior CAD Engineer – Physical Design Signoff

Intel Corporation; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Intel Corporation in Bengaluru, India seeks a Senior Physical Design Signoff Automation Engineer to develop and deploy automated signoff methodologies for advanced CPU and SoC designs. You will work with Physical Design, Timing, Power, Reliability, and CAD teams to improve signoff quality and productivity.

The role requires 8+ years in Physical Design/Signoff and strong scripting skills in Python, Tcl, and shell.

Qualifications

• M.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field.
• 8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation.
• Strong proficiency in Python, Tcl, and shell scripting.
• Experience with advanced process technologies (3nm, 2nm) and Intel 18A/14A.
• Exposure to CPU core, high-performance compute, or large SoC designs.
• Familiarity with AOCV/POCV and variation-aware timing methodologies.

Responsibilities

• Develop and enhance automation solutions for signoff flows, including RC extraction, STA, ERC, and power integrity signoff.
• Create scalable automation frameworks to reduce signoff turnaround time and improve engineering productivity.
• Develop scripts and tools to automate signoff checks, debugging, reporting, and data analysis.
• Analyze and resolve timing, extraction, ERC, and power signoff issues in collaboration with design teams.
• Drive methodology improvements to improve signoff convergence, quality, and correlation across implementation stages.
• Partner with EDA vendors and internal CAD teams to evaluate and deploy new signoff capabilities.
• Build dashboards and reporting infrastructure to monitor signoff health and project readiness.

Skills

Python

Tcl

Shell scripting

Machine Learning

Education

M.Tech / MS in Electrical Engineering or related

Tools

Parasitic Extraction

STA

ERC

Power Integrity signoff

Job description

Job Description:

We are looking for a highly motivated Senior Physical Design Signoff Automation Engineer to develop and deploy signoff methodologies and automation solutions for advanced CPU and SoC designs. The candidate will work closely with Physical Design, Timing, Power, Reliability, and CAD teams to improve signoff quality, productivity, and turnaround time. The ideal candidate possesses deep expertise in Parasitic Extraction, Static Timing Analysis (STA), Electrical Rule Checking (ERC), and Power Integrity signoff, along with strong programming and automation skills. Key Responsibilities Develop and enhance automation solutions for Physical Design signoff flows, including: RC Extraction Static Timing Analysis (STA) Electrical Rule Checking (ERC) Power Integrity (IR Drop/EM) Signal Integrity (SI) Create scalable automation frameworks to reduce signoff turnaround time and improve engineering productivity. Develop scripts and tools to automate signoff checks, debugging, reporting, and data analysis. Analyze and resolve timing, extraction, ERC, and power signoff issues in collaboration with design teams. Drive methodology improvements to improve signoff convergence, quality, and correlation across implementation stages. Partner with EDA vendors and internal CAD teams to evaluate and deploy new signoff capabilities. Build dashboards and reporting infrastructure to monitor signoff health and project readiness.

Qualifications:

Minimum Qualifications M.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field. 8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation. Strong proficiency in: Python Tcl Shell scripting Preferred Qualifications Experience working on advanced process technologies (3nm, 2nm, Intel 18A/14A, or equivalent). Understanding of AOCV/POCV and variation-aware timing methodologies. Familiarity with power delivery networks, EM analysis, and reliability signoff. Experience in Machine-learning methods and Agentic AI systems to solve CAD problems Exposure to CPU core, high-performance compute, or large SoC designs. Experience with distributed computing environments and large-scale signoff infrastructure.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

* Job posting details (such as work model, location or time type) are subject to change.

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