Senior ASIC/SoC Synthesis and Timing Constraints Engineer

Renesas Electronics India Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 9,000,000; Full time

Job summary

Renesas Electronics India Pvt Ltd is seeking a Staff/Senior Staff Engineer to join its ASIC/SoC Implementation team in Bengaluru. You will lead timing constraint development and RTL synthesis, collaborating with Architecture, RTL Design, Physical Design, and STA teams to deliver high-quality implementations on advanced processes.

The role requires 10–15 years in ASIC/SoC, expert knowledge of Design Compiler and Fusion Compiler, and strong scripting in Tcl or Python.

Qualifications

• Bachelor's or Master's degree in Electronics/Electrical Engineering.
• 10–15 years of experience in ASIC/SoC implementation.
• Expert knowledge of Synopsys Design Compiler and Fusion Compiler.
• Strong understanding of STA, timing closure, and SDC methodology.
• Hands-on scripting in Tcl and/or Python.
• Experience with advanced‑node implementation flows.
• Strong analytical, problem-solving, and debugging skills.
• Ability to work with global cross-functional teams.

Responsibilities

• Define, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.
• Drive RTL synthesis and optimization using Design Compiler and Fusion Compiler.
• Analyze and resolve timing, area, power, and implementation challenges to meet design targets.
• Collaborate with cross-functional teams to ensure robust design convergence.
• Develop and enhance methodologies, flows, and automation to improve productivity and design quality.
• Support timing closure activities and drive best practices for synthesis and constraint management.
• Debug and resolve synthesis and timing-related issues during project execution.
• Contribute to flow improvements for advanced-node ASIC/SoC development.

Skills

Synopsys Design Compiler

Fusion Compiler

STA

Timing constraints (SDC)

Tcl scripting

Python scripting

ASIC/SoC implementation

Cross-functional teamwork

Education

Bachelor's or Master's degree in Electronics/Electrical Engineering

Job description

Staff/Senior Staff Engineer, Synthesis & Timing Constraints

Company Description Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies. Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

Job Description

We are looking for an experienced Synthesis and Timing Constraints Engineer to join our ASIC/SoC Implementation team. In this role, you will lead timing constraint development and synthesis methodologies for complex SoC designs, working closely with Architecture, RTL Design, Physical Design, and STA teams to deliver high-quality implementations across advanced technology nodes.

Key Responsibilities

• Define, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.
• Drive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.
• Analyze and resolve timing, area, power, and implementation challenges to achieve design targets.
• Collaborate with cross-functional teams to ensure robust design convergence throughout the implementation cycle.
• Develop and enhance methodologies, flows, and automation to improve productivity and design quality.
• Support timing closure activities and drive best practices for synthesis and constraint management.
• Debug and resolve synthesis and timing-related issues during project execution.
• Contribute to flow improvements for advanced-node ASIC/SoC development.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
• 10-15 years of experience in ASIC/SoC implementation.
• Expert knowledge of Synopsys Design Compiler and Fusion Compiler.
• Strong understanding of Static Timing Analysis (STA), timing closure, and SDC methodology.
• Hands‑on scripting experience in Tcl and/or Python.
• Experience with advanced‑node implementation flows.
• Strong analytical, problem‑solving, and debugging skills.
• Ability to work effectively with global cross‑functional teams.

Preferred Qualifications

• Experience with low‑power design methodologies and optimization techniques.
• Knowledge of Physical Design and signoff flows.
• Familiarity with hierarchical and full‑chip implementation methodologies.
• Successful experience supporting complex SoC tapeouts.

Why Join Us?

Be part of a high‑performing implementation team working on next‑generation semiconductor products. You'll have the opportunity to influence methodology, drive technical innovation, and contribute directly to successful tapeouts on cutting‑edge process technologies.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

• We believe in rewarding our employees with a competitive benefits package alongside their salary.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .

Experience Level Senior Level