Senior ASIC Physical Design Engineer

AMD; Bengaluru; On-site; INR 1,400,000 - 3,000,000; Full time

Job summary

AMD in Bengaluru, India seeks a driven Physical Design Lead to steer next-generation ASICs from RTL to GDS2. You will drive floorplanning, placement, routing, CTS, timing closure and sign-off, coordinating with SOC architects, CAD and design teams to deliver top performance and power efficiency.

The role requires 8+ years in physical design and deep flow expertise. Ideal candidates have hands-on experience with Synopsys tools (Fusion Compiler, Design Compiler, PrimeTime) and Calibre, plus

Qualifications

• 8+ years of experience in physical design, preferably with high performance designs.
• Experience in automated synthesis and timing-driven place and route for RTL blocks.
• Experience in clock tree synthesis, power gating techniques, scan stitching and timing/power/area optimization.
• Experience in floorplanning, IP integration, checks for logic equivalence, and final signoff for large IP delivery.
• Strong tools experience for synthesis, PNR, timing analysis, and DRC/LVS checks; familiarity with schematic/layout tools.
• Scripting versatility to automate design flows; strong communication across geographically distributed teams.
• Experience with FinFET and multi-nm nodes; solid computer architecture understanding; strong problem solving.

Responsibilities

• Implement RTL to GDS2 flow and manage floorplanning for ASICs.
• Lead physical design optimization to deliver top performance/area and power efficiency.
• Drive floorplanning, placement, routing, CTS, timing closure and sign-off.
• Coordinate with SOC architects, CAD and design teams; drive design flows.
• Handle multiple PNR tools and ensure design quality across blocks.
• Develop and maintain flow scripts; identify complex technical problems and present solutions.

Skills

Physical Design Lead

ASIC Flow

Floorplanning

Timing Closure

Power Integrity

PNR Tools

Scripting

Education

BS/MS in EE or CS

Tools

Synopsys Fusion Compiler

ICC2

Design Compiler

PrimeTime

StarRC

Calibre

Redhawk

Genus

Innovus

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements.

Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.

The Person

AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions.

Key Responsiblities

• Implementing RTL to GDS2 flow
• Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence
• Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.
• Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off
• Identify complex technical problems, break them down, summarize multiple possible solutions,
• Drive and hands-on flow development and scripting

Preferred Experience

• 8+years of professional experience in physical design, preferably with high performance designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm
• Excellent physical design and timing background.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.

Academic Credentials

BS or MS degree in in Electrical Engineering or Computer Science. 8+years of experience in physical design role leading to an understanding of RTL to GDS development.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.