Senior ASIC Design Engineer

Nokia; Bengaluru; On-site; INR 12,00,000 - 18,00,000; Full time

Job summary

A leading technology company in Bengaluru is seeking an ASIC Design Engineer to work on cutting-edge chips for the Coherent Optics market. The ideal candidate will have a Bachelor's or Master's degree in Electrical or Computer Engineering, at least 5 years of relevant experience, and strong skills in scripting, RTL design, and synthesis. This position offers the opportunity to work with industry-leading technologies in a collaborative environment.

Qualifications

• Minimum 5 years of experience in ASIC design.
• At least 2 years of experience in RTL design.
• Strong experience in Synthesis, STA, and constraints development.

Responsibilities

• Develop and maintain CAD flows for ASIC design.
• Automate design flows using scripting languages.
• Identify and implement improvements in existing design methodologies.

Skills

Scripting languages (Python, Perl)

RTL design

Synthesis experience

Problem-solving skills

Communication skills

Education

Bachelor's or Master’s degree in Electrical or Computer Engineering

Tools

Synopsys EDA tools

LSF

Verilog or SystemVerilog

Job description

Overview

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise.

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

Responsibilities

• Work as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market.
• As a member of the ASIC design team, you will play the role to automate CAD flows for ASIC design. The candidate develops and maintains key common RTL IP modules used at every product generation. Interacts with RTL designers to understand the flow of work, develops the architecture to automate the flow and then implements the automation to eliminate pain points and errors to de-risk projects.
• Develop Synthesis flows and run synthesis alongside other designers and provide feedback to designers to improve timing and power.
• Develops scripts to automate using Python, Perl or other scripting languages.
• Works as part of a methodology team to develop new CAD/methodologies or flows which improve quality of design, reduce design time and provide consistent and reliable results across users and sites and streamline the process of ASIC development.
• Identifies input variables, categorizing them as fixed or customizable or user controllable options allowing users to have simplified interaction with the tool flow.
• Identifies scope for improvement in existing flows and implements those improvements.
• Works with experts and users across sites to identify new methodologies for development and adoption.
• Works with EDA tool vendors to identify options available across tools which reduce debug and development effort, and makes them available in a simplified way to design engineers.
• Evaluates new tools and new features from EDA tool vendors.
• Develops flows, takes them through a proof-of-concept on a project, and releases the flow for production use across teams and sites.
• Makes presentations to teams to ramp users about improvements or new flow development.
• Works on EDA tool installation and support, compute platform support, LSF job submittal support, and infrastructure-related support for worldwide ASIC design community. Collaborates with IT to debug and implement solutions. Continuously monitor/improve CAD infrastructure efficiency and CAD automation.

Qualifications

• Hold a Bachelor or master’s degree in electrical or computer engineering.
• Have a minimum 5 years of experience with relevant experience.
• Have a minimum 2 years of RTL design experience.
• Strong experience in Synthesis, STA and constraints development.
• Strong working experience of Shell, Perl, TCL and other programming/scripting languages.
• Strong problem-solving skills.
• Good verbal/written communication skills and teamwork.
• Knowledge of Synopsys Electronic Design Automation (EDA) tools is an asset.
• Knowledge of Verilog or SystemVerilog.
• Knowledge of LSF.
• Knowledge of machine learning and/or neural networks may be an asset.