R&D Engineering, Sr Engineer

Synopsys Inc; Khordha; On-site; INR 2,400,000 - 3,600,000; Full time

Job summary

Synopsys Inc. in India is seeking a Senior Application Engineer to support SLM PVT Monitor IP customers worldwide. The role focuses on integration, verification, timing closure, physical implementation, and testing of complex mixed-signal and digital IPs.

You will be the primary technical interface between customers and the PVT IP R&D group, providing expert guidance on IP integration, silicon bring-up, debug, validation, and production sign-off.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years in SoC or semiconductor IP: IP/SoC integration, RTL, design verification, physical design, timing/Liberty, DFT/ATPG.
• Ability to debug simulation mismatches and distinguish testbench or model limits from RTL defects.

Responsibilities

• Drive customer enablement for RTL-to-silicon integration of hard macros and PVTC controllers.
• Advise on floor planning, placement, routing, shielding, IR drop, and signal integrity for IP integration.
• Support timing closure and sign-off across IP boundaries, including STA, Liberty/SDF, and variation modelling.
• Provide DFT and production test support, including scan, ATPG, ATE strategies, and silicon validation.
• Assist with verification, bring-up, debug, low-power validation, and firmware integration.
• Translate calibration and accuracy requirements into practical firmware and test solutions.
• Troubleshoot customer issues, perform root-cause analysis, reproduce failures, and drive resolution with R&D teams.
• Partner with sales, IP development, validation, and documentation teams to support new releases.

Skills

RTL & SystemVerilog

Debugging & root-cause analysis

Customer-facing communication

Mixed-signal IP integration

Technical English writing

Education

Bachelor’s in Electrical/Computer Engineering

Master’s degree (preferred)

Tools

VCS

Verdi

Fusion Compiler

PrimeTime

SpyGlass

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

We are seeking a Senior Application Engineer to support Synopsys SLM PVT Monitor IP customers worldwide. The ideal candidate will have hands-on experience in the integration, verification, timing closure, physical implementation, and testing of complex mixed-signal and digital IPs This customer-facing role acts as the primary technical interface between global semiconductor customers and the PVT IP R&D organization, providing expert guidance on IP integration, silicon bring-up, debug, validation, and production sign-off.

What You'll Need

• Drive customer enablement for RTL-to-silicon integration of hard macros and PVTC controllers.
• Advise on floor planning, placement, routing, shielding, IR drop, and signal integrity for optimal IP integration.
• Support timing closure and sign-off across IP boundaries, including STA, Liberty/SDF, and variation modelling methodologies.
• Provide DFT and production test support, including scan, ATPG, ATE strategies, and silicon validation.
• Assist with verification, bring-up, debug, low-power validation, and firmware integration.
• Translate calibration and accuracy requirements into practical firmware and test solutions.
• Troubleshoot customer issues, perform root-cause analysis, reproduce failures, and drive resolution with R&D teams.
• Partner with sales, IP development, validation, and documentation teams to support new releases, interoperability initiatives, and technical customer engagement.

Who You Are

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years in SoC or semiconductor IP in several of: IP/SoC integration, RTL (Verilog/SystemVerilog), design verification, place-and-route / physical design, timing/Liberty, DFT/ATPG.
• Ability to debug simulation mismatches (X/Z, handshake stalls, model vs. netlist) and to distinguish testbench or model limits from RTL defects.
• Working knowledge of STA using .lib/.db/SDF, including constraint arcs (setup/hold).
• Working knowledge of scan architecture and ATPG deliverables vs. functional simulation.
• Ability to work strictly from specifications and state what is specified vs. customer-owned.
• Strong written English for customer-facing technical answers.
• Familiarity with Synopsys tools (VCS, Verdi, Fusion Compiler, PrimeTime, SpyGlass/VC Static).
• Customer-facing AE, FAE, design services, or IP applications experience.
• Mixed-signal or analog-aware digital integration (ESD, analog test pins, supply sequencing).
• Advanced-node (FinFET) SoC and IP delivery.
• Master’s degree in a related field.

The Team You'll Be Part Of

You will join the ACE Global Technical Support team, a diverse group of talented engineers and subject matter experts dedicated to enabling customer success through simulation-driven innovation. The team collaborates closely across regions and disciplines to help customers maximize the value of Synopsys simulation technologies while advancing best practices in engineering analysis, AI-assisted workflows, and customer support excellence.