Analog Design, Sr Engineer

Synopsys; Dadri; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Synopsys India seeks a detail-oriented semiconductor engineer to own IP characterization and library release flows, generating Liberty, Verilog, LEF, CDL, GDS, APL, and related views while improving automation.

You will collaborate with design, layout, CAD, and product engineering teams to validate deliverables and drive quality across technology nodes, enabling robust IP readiness for customer SoCs.

Qualifications

• Must know Liberty modeling and related views (NLDM/NLPM, CCS timing/power, variation modeling).
• Hands-on experience generating/validating EDA deliverables: Liberty, Verilog, LEF, CDL, GDS, ATPG, IBIS, APL, CMM, NDM.
• Strong scripting for automation (Python/Perl/Tcl/Shell) and QA.

Responsibilities

• Generate, validate, package, and release IP libraries and EDA deliverables.
• Develop and maintain characterization flows for Liberty models and related views.
• Create and enhance automation to optimize characterization, view generation, validation, and release processes.

Skills

IP characterization

EDA deliverables

Flow automation

Scripting

Debugging

Communication

Team collaboration

Version control

Tools

Liberty .lib

Verilog

LEF

CDL

GDS

ATPG

IBIS

APL

CMM

NDM

NLDM

NLPM

CCS Timing

CCS Power

Variation modeling

Automation scripts

Job description

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are

You are a detail-oriented semiconductor engineer with strong experience in IP enablement, characterization, CAD view generation, and library release flows. You possess in-depth knowledge of standard EDA deliverables and understand how they are consumed across downstream SoC implementation, verification, test, and signoff flows.

You are passionate about delivering high-quality IP releases and have hands-on expertise in generating, validating, and packaging views such as Liberty (.lib), Verilog, LEF, CDL, GDS, NDM, IBIS, ATPG, APL, and CMM. You enjoy solving complex technical challenges through scripting and automation and are continuously looking for opportunities to improve methodology, efficiency, and quality.

You thrive in collaborative environments, working closely with design, layout, CAD, product engineering, validation, and customer support teams to ensure accurate and timely IP deliverables. Your analytical mindset, strong debugging skills, and commitment to quality make you a valuable contributor to the success of complex semiconductor products.

What You'll Be Doing

• Generate, validate, package, and release General Purpose and Specialty I/O libraries and associated EDA deliverables.
• Develop and maintain characterization flows for generating Liberty (.lib) models, including NLDM, NLPM, CCS Timing, CCS Power, variation modeling, and related views.
• Generate and validate industry-standard EDA views including NDM, LEF, Verilog, CDL, GDS, ATPG, IBIS, APL, CMM, and other customer deliverables.
• Perform quality assurance checks to ensure accuracy, consistency, and completeness of IP deliverables before release.
• Work closely with design and layout teams to understand circuit functionality, architecture, and flow requirements.
• Develop, maintain, and enhance automation scripts to optimize characterization, view generation, validation, and release processes.
• Establish and improve methodologies for view generation, validation, and packaging across various technology nodes and IP products.
• Investigate, debug, and resolve customer-reported issues related to IP deliverables and EDA views.
• Contribute to continuous improvements in IP development flows, methodologies, and release infrastructure.
• Support cross-functional teams by providing technical expertise on library models, EDA views, and downstream SoC integration requirements.

The Impact You Will Have

• Enable successful integration of Synopsys IP into customer SoCs through accurate and high-quality EDA deliverables.
• Improve product quality and customer satisfaction by delivering validated and production-ready IP release packages.
• Drive efficiency and scalability through automation and methodology enhancements.
• Accelerate design cycles by ensuring reliable characterization and EDA view generation processes.
• Reduce customer-reported issues through robust QA and validation methodologies.
• Strengthen Synopsys' reputation as a provider of high-quality semiconductor IP solutions.
• Contribute to continuous innovation in IP deployment methodologies and CAD infrastructure.

What You'll Need

• Strong understanding of semiconductor IP characterization and library generation flows.
• Hands-on experience generating and validating EDA deliverables such as Liberty (.lib), Verilog, LEF, CDL, GDS, ATPG, NDM, IBIS, APL, CMM, and related views.
• Knowledge of Liberty modeling methodologies including NLDM, NLPM, CCS Timing, CCS Power, and variation modeling concepts.
• Understanding of how characterization data and CAD views are used in synthesis, place-and-route, STA, DFT, simulation, and SoC implementation flows.
• Proficiency in scripting languages such as Python, Perl, Tcl, or Shell for flow automation and validation.
• Experience working with design, layout, CAD, and product engineering teams in semiconductor development environments.
• Strong debugging and problem-solving skills with the ability to analyze and resolve customer-reported issues.
• Excellent communication skills and the ability to collaborate effectively across global teams.
• Familiarity with IP release methodologies, quality assurance processes, and version control systems is highly desirable.

Who You Are:

• An analytical thinker with excellent problem-solving skills and keen attention to detail.
• A collaborative team player who values diversity, inclusion, and open communication.
• A proactive learner who stays current with industry trends and emerging technologies.
• An effective communicator, able to translate complex technical information to diverse audiences.
• A results-driven individual who is adaptable, resilient, and comfortable with fast-paced, high-impact work.

The Team You’ll Be A Part Of:

You’ll join a passionate, multidisciplinary team of analog and mixed-signal engineers dedicated to advancing Synopsys’ interface IP portfolio. The team is focused on delivering robust, innovative, and high-quality solutions that meet the rigorous demands of a global customer base. Collaboration, continuous improvement, and technical mentorship are at the core of our culture, ensuring you’ll have the support and opportunities needed to thrive and grow.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.