QKD Chip designer

SuperQ Technologies India Pvt Ltd; Bengaluru; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

SuperQ Technologies India Pvt Ltd. seeks a QKD Chip Designer to conceptualize and layout photonic integrated circuits, migrating bulky quantum optical setups into compact PICs.

The role focuses on chip-level and system-level design for quantum protocols (BB84, E91) and requires 2–5+ years in PIC design with strong EM/photonic solver skills. Bengaluru office, on-site collaboration with RF/electronic teams.

Qualifications

• Master's or PhD in Electrical Engineering, Photonics, Physics, or Quantum Engineering.
• 2–5+ years hands‑on PIC design, semiconductor tape‑outs, or quantum hardware engineering.

Responsibilities

• Model and optimize on‑chip photonic components (waveguides, MZI, beam splitters, phase shifters, grating couplers).
• Design chip layouts minimizing insertion loss and crosstalk while preserving polarization/phase stability.
• Translate simulations into GDS layouts using EDA/PDA tools and align with PDks.
• Coordinate with foundries for fabrication and perform DRC/LVS/ERC checks.
• Integrate photonic chip with high‑speed control electronics, pulse generators, and single‑photon detectors.
• Collaborate with test/characterization labs to refine models against fabricated chips.

Skills

EM & photonics solvers

KLayout

Luceda IPKISS

Nazca

Cadence/Synopsys

Python

MATLAB

BB84 & QKD protocols

Quantum optics

Single-photon dynamics

Education

Master's or PhD in Electrical Engineering or Photonics

Tools

Ansys HFSS

Lumerical

Tidy3D

Cadence/Synopsys design suites

Job description

The QKD Chip Designer leads the conceptualization and layout of chip-scale quantum cryptography hardware. The primary focus is migrating large, bulky, table-top quantum optical setups (lasers, beam splitters, and modulators) into compact, manufacturable Photonic Integrated Circuits (PICs) or specialized silicon chips.

This hardware executes quantum protocols like BB84 or E91 to establish secure communication keys.

Key Responsibilities

Component-Level Simulation: Model and optimize active and passive on- chip photonic components—such as waveguides, Mach-Zehnder interferometers, beam splitters, phase shifters, and grating couplers.

System-Level Architecture: Design chip layouts that minimize insertion loss, manage optical/RF crosstalk, and maintain polarization or phase stability required to preserve fragile quantum states.

Layout & Tape-Out (GDSII): Translate successful simulations into physical mask layouts using specialized Electronic Design Automation (EDA) and Photonic Design Automation (PDA) tools, ensuring compliance with foundry Process Design Kits (PDKs).

Foundry & Fab Validation: Run industry-standard physical validation checks (DRC, LVS, ERC) and coordinate with external semiconductor foundries for chip fabrication.

Hardware Integration: Work with electronic and FPGA engineers to integrate the photonic chip with high-speed control electronics, pulse generators, and single-photon detectors.

Iterative Loop & Testing: Collaborate with the characterization lab team to compare experimental data from fabricated chips against your simulations, refining design models based on real-world yields and fabrication variations.

Technical Skills & Tools

Simulation Software: Proficiency in electromagnetic (EM) and photonics solvers such as Ansys HFSS, Lumerical (FDTD/MODE), Synopsys RSoft, or Tidy3D.

Layout & EDA Tools: Experience with KLayout, Luceda IPKISS, Nazca, or Cadence/Synopsys suites for generating GDS layouts.

Programming: Scripting languages—primarily Python or MATLAB—for automated design sweeps, data analysis, and inverse design algorithms.

Quantum Protocol Literacy: Solid grasp of quantum optics, single-photon dynamics, and standard QKD protocols (BB84, decoy-state, or continuous-

variable QKD).

Education & Experience

Education: A Master's or Ph.D. in Electrical Engineering, Photonics, Physics, or Quantum Engineering.

Experience: Typically requires 2–5+ years of hands‑on experience in PIC design, semiconductor tape‑outs, or quantum hardware engineering.