Principal Timing Signoff Engineer

Synopsys Ind pvt ltd; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Synopsys India Pvt Ltd in Bengaluru seeks an experienced Timing Signoff Expert to drive timing signoff methodologies for standard cell libraries across advanced nodes. You will own signoff methodology, validate setup/hold, low-VDD, MCMM environments, and ensure robust correlation to silicon.

Collaboration with characterization, CAD, modeling, and customer-facing engineering teams is essential. You will mentor engineers and contribute to documentation and best practices.

Qualifications

• 15+ years in semiconductor industry focusing on timing signoff and standard cell libraries.
• Expert in STA and signoff methodologies for advanced process technologies.
• Experience driving signoff strategy across multiple nodes including N7/N5/N3.
• Deep Liberty modeling and LVF/POCV/SOCV/statistical timing knowledge.
• Track record deploying signoff methodologies across products/customers.

Responsibilities

• Own and develop timing signoff methodologies for standard cell libraries.
• Validate setup/hold, recovery/removal, pulse-width, noise margins.
• Drive MCMM, low-VDD signoff robustness, and yield optimization.
• Correlate nominal, statistical, and silicon timing results.
• Lead root-cause investigations and provide corrective actions.
• Support customers with timing signoff issues and provide guidance.

Skills

STA

Signoff methodologies

Liberty modeling

Variation modeling

Timing signoff

ECAD tools

Python

Tcl

Linux

Root-cause analysis

Tools

SiliconSmart

Liberate

HSPICE

Spectre

FineSim

Job description

Organization: Standard Cell Library Development Team

Technology Focus: Advanced TSMC Nodes (N3/N2/N5/N7 and derivatives)

Position Summary

We are seeking an experienced Timing Signoff Expert to drive timing signoff methodology, validation, and quality for standard cell libraries across multiple TSMC technology nodes. The candidate will play a key role in ensuring library timing accuracy, correlation to silicon, and robust signoff methodologies that enable successful deployment of standard cell libraries for high-performance, low-power, and AI/compute SoCs.

This role requires deep expertise in STA, Liberty characterization, variation modeling, timing signoff methodologies, and advanced-node design challenges. The candidate will collaborate closely with characterization, CAD, modeling, design methodology, and customer-facing engineering teams.

Timing Signoff Methodology

• Own and develop signoff methodologies for standard cell libraries across advanced technology nodes in close collaboration with foundry
• Define and validate setup, hold, recovery/removal, pulse-width, and noise margins w.r.to signoff criteria.
• Develop signoff guidelines for low-VDD, multi-corner, multi-mode (MCMM) environment for timing robustness and yield optimization
• Drive methodology improvements for advanced variation-aware timing analysis.
• Define and drive improvements for signoff recommendations with clear data backed justification
• Analysis of correlation between nominal, statistical, and silicon behavior.
• Root-cause signoff discrepancies and define corrective actions.
• Improve timing prediction accuracy through enhanced modeling techniques.

Customer Support & Escalations

• Support internal and external customers on timing signoff issues.
• Debug critical customer-reported timing correlation problems.
• Provide recommendations for deployment of signoff libraries.
• Create technical documentation and best-practice guidelines.

Required Qualifications

• 15+ years of semiconductor industry experience, including significant experience in timing signoff, standard cell library development, characterization, and advanced-node methodology development.
• Recognized technical expert in Static Timing Analysis (STA) and signoff methodologies for advanced process technologies.
• Demonstrated experience driving timing signoff strategy for multiple technology nodes, preferably including TSMC N7, N5, N3 and beyond.
• Deep expertise in Liberty modeling, characterization quality assessment, LVF, AOCV, POCV, SOCV, and statistical timing methodologies.
• Proven track record of defining and deploying signoff methodologies used across multiple products, customers, or business units.
• Strong understanding of advanced-node timing challenges including:
• Low-VDD operation
• Variation-aware signoff
• Aging (BTI/HCI) effects
• Clock variation and CRPR
• Yield-aware timing optimization
• Extensive experience correlating Liberty models, STA results, SPICE simulations, and silicon measurements to drive signoff accuracy.
• Expert-level proficiency with industry-standard EDA tools such as:
• SiliconSmart or Liberate
• HSPICE, Spectre, FineSim
• Parasitic extraction and correlation tools
• Strong automation and software development skills in Tcl, Python, and Linux environments, with experience building scalable signoff and QA infrastructure.
• Proven ability to lead complex root-cause investigations involving timing correlation, characterization quality, customer escalations, and silicon validation.
• Experience working directly with strategic customers to define deployment guidelines, resolve critical signoff issues, and influence future methodology requirements.
• Demonstrated capability to lead cross-functional engineering initiatives spanning characterization, library design, CAD, modeling, EDA vendors, and customer support teams.
• Strong mentoring and technical leadership skills with experience growing and coaching senior engineers and technical leads.
• Excellent communication and presentation skills, including the ability to influence senior management, customers, and industry partners on signoff methodology direction.