Principal ASIC Design Engine

NXP Semiconductors; Hyderabad; Vor Ort; INR 3.000.000 - 6.000.000; Vollzeit

Zusammenfassung

NXP Semiconductors in Hyderabad is seeking a Principal ASIC Design Engineer with deep RTL design expertise for AI inference accelerators. You will drive micro-architecture development, RTL implementation, and integration across architecture, verification, DFT, physical design, firmware, and system teams.

The role requires SystemVerilog/Verilog mastery, clock/reset architecture knowledge, low-power techniques, and performance-driven implementation.

Qualifikationen

• 14+ years of experience in ASIC/SoC RTL design.
• Strong Verilog/SystemVerilog coding skills.
• Solid understanding of synthesis, timing analysis, and power analysis.
• Experience with lint, CDC, and RDC flows.
• Strong debugging and root-cause analysis skills.

Aufgaben

• Define and implement hardware architectures optimized for AI inference SoCs.
• Contribute to microarchitecture definition and evaluate design trade-offs for complex SoCs, including custom ISA-based processors, high-speed interconnects, and high-bandwidth I/O.
• Own features end to end, from specification and RTL through integration, synthesis, and debug.
• Collaborate with physical design teams on synthesis, timing closure, and power optimization.
• Work with the verification team to ensure design correctness.
• Partner with architecture engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.

Kenntnisse

Verilog/SystemVerilog

Synthesis

Timing analysis

Power analysis

Debugging

Tools

Lint

CDC

RDC flows

Jobbeschreibung

Principal ASIC Design Engineer - Digital Design

Primary Location: Hyderabad

Role Summary

We are seeking an experienced RTL Designer with strong expertise in micro-architecture development, RTL design, integration, and implementation of complex digital blocks/subsystems. The ideal candidate will have a proven track record of translating architectural specifications into high-quality RTL, driving designs from concept through synthesis and silicon bring-up, and collaborating closely with architecture, verification, DFT, physical design, firmware, and system teams. The role requires deep knowledge of System Verilog/Verilog RTL design, digital design fundamentals, clock/reset architectures, low-power design techniques, and performance-driven implementation. The candidate should be capable of owning IP/block-level development, resolving functional and timing issues, supporting verification and implementation activities, and ensuring delivery of robust, power-efficient, and high-performance designs for next-generation AI inference accelerators.

Job Responsibilities

• Define and implement hardware architectures optimized for AI inference SoCs.
• Contribute to microarchitecture definition and evaluate design trade-offs for complex SoCs, including custom ISA-based processors, high-speed interconnects, and high-bandwidth I/O.
• Own features end to end, from specification and RTL through integration, synthesis, and debug.
• Collaborate with physical design teams on synthesis, timing closure, and power optimization.
• Work with the verification team to ensure design correctness.
• Partner with architecture engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.

Job Qualifications

• 14+ years of experience in ASIC/SoC RTL design.
• Strong Verilog/SystemVerilog coding skills.
• Solid understanding of synthesis, timing analysis, and power analysis.
• Experience with lint, CDC, and RDC flows.
• Strong debugging and root-cause analysis skills.

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

For more information, visit www.nxp.com.

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