Principal Application Engineer, VC Formal

Synopsys, Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Synopsys, Inc. is seeking a senior verification professional to lead deployment of VC Formal solutions at customer sites, analyzing designs to target formal checks and optimizing test benches for proof closure.

You will train teams, collaborate with R&D, and drive adoption of formal methodologies across complex SoC and IP designs. Deep RTL and SystemVerilog knowledge is essential.

Qualifications

• 10 to 15 years of hands-on experience in digital design verification.
• Deep expertise in formal verification methodologies.
• Strong understanding of RTL design and SystemVerilog.
• Experience in customer-facing consulting or field engineering is required.

Responsibilities

• Lead technical deployment of VC Formal solutions at customer sites, assessing verification environments and recommending formal methodologies tailored to their design challenges
• Analyze customer design blocks to identify targets for formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking
• Diagnose root causes of tool performance issues and optimize formal test benches to achieve proof closure
• Develop and deliver technical training to customer teams on VC Formal features and best practices
• Collaborate with Synopsys R&D and product engineering to relay customer priorities affecting product roadmap
• Support customers in applying formal verification to complex logic including data path verification and math functions

Skills

Digital design verification

Formal verification methodologies

RTL design

SystemVerilog

Customer engagement

Tools

VC Formal

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade or more in verification and you know that formal is not a checkbox, it is the difference between finding a corner case bug in week two or in production six months later. You walk into a customer site, look at their design blocks and test benches, and see the problem underneath the symptoms. You ask questions that get to root cause, not surface noise.

You have debugged enough performance bottlenecks to know when the issue is the tool, the model, or the design itself, and you can explain the tradeoff in terms the design team will understand. You are comfortable presenting to senior engineers and equally comfortable rolling up your sleeves to optimize a formal test bench that is choking on state space explosion.

At Synopsys, you will work directly with customers building the most complex chips in the industry, and what you recommend will shape how they verify their designs.

What You'll Be Doing

• Lead technical deployment of VC Formal solutions at customer sites, assessing verification environments and recommending formal methodologies tailored to their design challenges
• Analyze customer design blocks to identify the right targets for formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking
• Diagnose root causes of tool performance issues, including state space explosion and convergence problems, then optimize formal test benches to achieve proof closure
• Develop and deliver technical training to customer teams on new VC Formal features, product updates, and formal verification best practices
• Work directly with Synopsys R&D and product engineering teams to communicate customer priorities and technical requirements that influence product roadmap
• Support customers in applying formal verification to complex logic including data path verification, math functions, and sequential equivalence across design revisions

The Impact You Will Have

• Enable customers to find critical bugs earlier in the design cycle, reducing costly respins and time-to-market delays
• Drive adoption of formal verification methodologies that improve verification coverage and confidence across complex SoC and IP designs
• Shape the VC Formal product roadmap by translating real-world customer challenges into actionable engineering requirements
• Accelerate customer productivity by delivering training and methodologies that make formal verification accessible to teams with varying levels of expertise
• Build long-term technical relationships with leading semiconductor companies, becoming a trusted advisor on verification strategy
• Reduce tool performance bottlenecks and proof times through expert modeling and optimization, directly improving customer ROI

What You'll Need

• 10 to 15 years of hands-on experience in digital design verification, with deep expertise in formal verification methodologies
• Strong application knowledge of formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking
• Proven experience diagnosing and resolving formal tool performance issues, including convergence problems and proof optimization
• Solid understanding of RTL design, SystemVerilog, and verification test bench development
• Experience working directly with customers in a technical consulting, application engineering, or field engineering role
• Experience with VC Formal or equivalent formal verification tools is a strong plus

Who You Are

• You can walk into a customer meeting, listen to a verification challenge, and sketch out a formal methodology that makes immediate sense to the team
• You know when to push back on a customer request that will not solve the real problem, and you can explain why in terms they respect
• You are comfortable moving between deep technical debugging, writing formal properties, and presenting results to engineering leadership
• You treat every customer deployment like a learning opportunity, not just for them but for the product team back at Synopsys
• You are organized enough to manage multiple customer engagements at once and technical enough to go deep when a proof is failing

The Team You'll Be Part Of

Application engineers (AEs) drive and deploy SNPS technologies at the customers and support successful usage of the products at the customers that leads to renewals and new business.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.