PMIC Analog Design Lead

118-WW TMG MFG OPS; Bengaluru; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

118-WW TMG MFG OPS in Bengaluru seeks an experienced analog/mixed-signal IC designer to own PMIC design, from architecture to silicon bring-up. You will define architectures for Buck, Boost, SIMO converters and ensure high efficiency and performance for battery-powered devices.

You will collaborate with systems and applications teams, drive cross-functional reviews, and mentor junior engineers while delivering robust power-management solutions.

Qualifications

• 7+ years of analog/mixed-signal IC design experience with power management expertise.
• Deep hands-on experience with at least one Buck/Boost/SIMO converter in silicon.
• Strong layout and post-layout verification skills.

Responsibilities

• Design and deliver high-performance analog power converters meeting tight density and efficiency targets.
• Define PMIC system architecture translating customer requirements to silicon specs.
• Own full IC design flow from schematic to silicon bring-up and characterization.
• Lead cross-functional design reviews and mentor junior engineers.

Skills

Analog IC design

Power management

Converter design

Buck/Boost/SIMO

LDOs/Charge Pumps

Cadence Virtuoso

Education

Bachelor's in Electrical Engineering

Master's or PhD preferred

Tools

Cadence Virtuoso

Spectre

Simplis

AMS co-simulation

Job description

Change the world. Love your job.

In this role you will be choosing switching converter architectures for Buck, Boost, Buck-Boost, Inverting Buck-boost and SIMO converters, innovating to meet the best efficiency, transient-performance and IQ at high operational frequencies, to enable our customers to get the best battery life for hand-held electronic devices. Suitable candidates with proven experience in leading switching converter designs, track -record in pushing performance boundaries by way of innovation, an in-depth silicon debug experience should apply. Following are the key activities:

• Design and deliver high-performance analog power converter circuits - buck, boost, SIMOs, LDOs, and Charge Pumps - meeting aggressive targets for power density, efficiency, and transient performance
• Define PMIC system architecture and translate complex customer requirements into silicon specifications, driving alignment across design, systems, and applications teams
• Own technical execution across the full IC design flow: schematic capture, simulation, layout review, post-layout verification, silicon bring-up, and characterization
• Serve as primary technical owner for one or more converter blocks within multi-block PMIC products
• Lead cross-functional design reviews and ensure design quality, robustness, and reliability meet program and customer standards
• Collaborate with internal systems and architecture teams to resolve integration challenges and drive technical closure
• Mentor and support junior engineers on design methodology, tools, and best practices

Minimum requirements:

• Bachelor's degree in Electrical Engineering or related field (Master's or PhD preferred)
• 7+ years of analog/mixed-signal IC design experience with deep expertise in power management
• Strong hands-on experience designing at least one of Buck, boost, SIMO converter in silicon.
• Expert hands-on experience of LDOs, Charge Pumps, Boot Strap, Switch Cap circuits.
• Expert command of converter control architectures: Adaptive on Time, Constant on/off Time, peak/valley/average current mode control, control systems and compensations.
• Hands-on transistor-level design of integrated power FETs, gate drivers, oscillators, bandgap/bias circuits, error amplifiers, and frequency compensation networks
• High-efficiency design techniques: adaptive dead-time, DVS, multi-phase current balancing, light-load optimization, and IDDQ minimization at high switching frequencies
• Experience with multi-rail PMIC SoC integration: power sequencing, UVLO, OCP, OTP, and digital interfaces (I2C, SPI, MIPI I3C)
• Fully proficient and deeply comfortable with standard Power IC design flows end-to-end (Cadence Virtuoso, Spectre)
• Worst-case corner analysis, top-level and Monte Carlo simulation, and post-layout PEX sign-off
• Physical layout review: power routing, grounding, signal integrity, thermal management, and die area optimization
• Working knowledge of Simplis and AMS co-simulation flows required; hands-on expertise is a strong plus
• Strong knowledge of BCD and/or advanced CMOS process trade-offs for high-performance Power IC design
• Full-cycle IC design experience: schematic, simulation, layout collaboration, post-layout verification, silicon validation, and characterization
• Ability to work independently and drive technical decisions with confidence, and multi-task
• Strong written and verbal communication skills

Preferred qualifications:

• Experience of designing PMICs for consumer electronics (mobile, laptops, wearables)
• Experience in customer-facing technical alignment and specification negotiation
• Prior experience as a technical lead or design owner on a multi-block PMIC products for consumer electronics (mobile, laptops, wearables)
• Demonstrated ability to drive customer and cross-functional technical discussions with authority and ownership
• Proven track record of mentoring engineers through complex design challenges
• Ability to manage and personally execute multiple concurrent design tasks on aggressive schedules with high autonomy