Physical Design Lead with STA

AMD; Hyderabad; On-site; INR 4,000,000 - 6,400,000; Full time

Job summary

AMD Hyderabad is seeking an experienced Design Signoff engineer to own SubSystem PnR for a 10-partition SoC. You will lead RTL-to-GDS execution, coordinate with CAD and methodology teams across geographies, and drive first-pass silicon success.

The role requires strong scripting (Python/TCL/Makefile), deep CTS/Route/STA know-how, and the ability to present complex data clearly. Collaboration with multiple business units accelerates timing closures and flow improvements.

Qualifications

• 8+ years of design signoff/closure experience.
• Strong PnR background with problem solving for PPA and debug.
• Technical depth in CTS, Route, STA.
• EMIR driven power grid knowledge.
• PnR and STA signoff correlation drive and convergence.
• Scripting: TCL, Perl, Python, Makefile.
• Solve flow gaps and drive new requirements and methodology.
• Experience with Synopsys, Cadence, Mentor tools.
• AMD TileBuilder and lower tech nodes (5/3/2) is a plus.

Responsibilities

• Owns SS Partitions PnR execution and closure.
• Drive improvements in closure and PPA metrics.
• Analyze data and provide feedback to the Design team.
• Collaborate with PnR, CAD and methodology teams across geographies.
• Automate design signoff requirements and dashboards.
• Present complex technical information clearly to multi-level teams.
• Interact with internal AMD PPA teams and external interfaces.
• Identify best practices to update flow and project settings.

Skills

PnR background

SDC coding

TCL scripting

Python scripting

Perl scripting

Power aware design

CTS/Route/STA

Power grid knowledge

ML for physical design

EDA tools knowledge

Education

Bachelors/Masters in EE/CS

Tools

Synopsys Cadence Mentor tools

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

• As a member of the PD pnr team responsible for owning and leading SubSystem of 10 partitions. SoC SS PD closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for RTL to GDS execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

THE PERSON:

• A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.
• Strong self-driving ability, should have excellent communication skills (both written and oral)

KEY RESPONSIBILITIES:

• Owns SS Partitions PnR execution and closure
• Drive new improvement in closure
• Analysis of data and feedback to Design team
• Work with PnR team members for closure convergence starting from Synthesis to Route
• Closure signoff on STA, EMIR, PV
• Work and collaborate with different business units, CAD and central methodology team to drive the requirement
• Automation to refine and improve design signoff requirement and dashboarding
• Ability to organize and present complex technical information in a crisp and concise manner.
• Interact with other PPA (equivalent) teams internal to AMD
• Identify best practices across AMD and industry to update and improve flow/project settings
• To increase the competitiveness of each stage in AMD design flow
• Ability to work with multi-level functional teams across various geographies.
• Highly organized, strong affinity for automation and prioritization.

PREFERRED EXPERIENCE:

• 8+ year or more experience design signoff closure
• Strong PnR backround with critical problem solving ability on improving PPA and debug
• Technical depth in CTS, Route, STA.
• EMIR driven power grid knowledge
• PnR and STA signoff correlation drive and convergence
• Strong at SDC coding and debug skills
• Drive new requirements and methodology to aid timing closure at SoC
• Identify the gaps and support flows
• Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
• Drive team towards common requirements and flows
• Experienced in deploying and implementing ML techniques and algorithms in physical design.
• Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
• Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
• AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.