PD PNR Engineer

Advanced Micro Devices, Inc.; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD is seeking an MTS Silicon Design Engineer – Tile PnR to own end-to-end physical implementation of SoC/IP tiles, drive floorplanning, placement, timing, and ECOs, collaborating with RTL, architecture, and CAD teams.

The role emphasizes automation, milestone delivery, and mentorship of junior engineers, with a focus on delivering high-quality convergence and QoR improvements within tight project schedules.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, or related field.
• 7–10 years of experience in Physical Design or ASIC implementation.
• Hands-on experience with floorplanning, placement, CTS, routing, and timing closure.
• Strong understanding of STA concepts and signoff requirements.

Responsibilities

• Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff.
• Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization.
• Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets.
• Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration.
• Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges.
• Support milestone deliveries and ensure quality execution aligned with project schedules.
• Develop automation, scripts, and improved methodologies to enhance productivity and convergence efficiency.
• Mentor junior engineers and contribute to technical reviews, best practices, and knowledge sharing.

Skills

VLSI implementation flows

Scripting: Tcl/Python/Perl/Shell

Debugging & analytical skills

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Computer Engineering

Tools

Synopsys Fusion Compiler

ICC2

PrimeTime

RedHawk

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

MTS Silicon Design Engineer – Tile PnR

Role Summary

Responsible for end-to-end physical implementation and convergence of complex SoC/IP tiles. The engineer will drive floorplanning, place-and-route, timing closure, power and area optimization, physical verification readiness, and ECO implementation while collaborating closely with RTL, architecture, CAD, timing, clocking, and full-chip teams. Expected to independently own critical tiles, deliver high-quality milestones, and contribute to methodology and automation improvements.

Key Responsibilities

• Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff.
• Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization.
• Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets.
• Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration.
• Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges.
• Support milestone deliveries and ensure quality execution aligned with project schedules.
• Develop automation, scripts, and improved methodologies to enhance productivity and convergence efficiency.
• Mentor junior engineers and contribute to technical reviews, best practices, and knowledge sharing.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Computer Engineering, or related field.
• 7 to 10 years of experience in Physical Design or ASIC implementation.
• Strong understanding of digital design fundamentals and VLSI implementation flows.
• Hands‑on experience with floorplanning, placement, CTS, routing, timing closure, and ECO implementation.
• Good understanding of STA concepts, timing optimization, and physical design signoff requirements.
• Proficiency in scripting using Tcl, Python, Perl, or Shell.
• Strong debugging, analytical, and problem‑solving skills.
• Excellent communication and cross‑functional collaboration abilities.

Preferred Experience

• Experience in converging large and complex CPU, GPU, NOC, AI/ML, or networking tiles.
• Exposure to advanced technology nodes (5nm, 4nm, 3nm or below).
• Knowledge of power optimization, EMIR, CDC, RDC, and physical verification methodologies.
• Experience with Synopsys Fusion Compiler, ICC2, PrimeTime, RedHawk, or equivalent EDA tools.
• Proven track record of independently leading critical tiles and driving milestone deliveries.
• Experience in PPA optimization, methodology development, AI‑assisted PD flows, and automation initiatives.
• Ability to guide junior engineers and act as a technical lead for assigned tiles.
• #LI-BM2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.