NPU/AI Processor Synthesis Staff/ Sr Staff/ Technical Lead

QUALCOMM, Inc.; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

QUALCOMM, Inc. in Bengaluru seeks a NPU Synthesis Lead to drive RTL-to-gate synthesis and timing closure for NPU IP and subsystems in cutting-edge SoCs.

You will lead synthesis flows, optimize for PPA, and collaborate with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced nodes. Experience with Design Compiler, Genus, and PrimeTime is required.

Qualifications

• Experience in ASIC synthesis and timing closure.
• Proficient with RTL→Synthesis→STA→P&R flow.

Responsibilities

• Lead RTL-to-gate-level synthesis for NPU IP and subsystems.
• Drive pre-layout and post-layout timing closure across corners.
• Apply physical-aware synthesis techniques for PPA targets.
• Mentor junior engineers and coordinate with cross-functional teams.

Skills

ASIC design flow

RTL-to-Synthesis

Synthesis tooling

UPF/CPF flows

Tcl scripting

Python scripting

Perl scripting

Design Compiler

Genus

PrimeTime

Multi-voltage design

Leadership

Education

Bachelor’s/Master’s in Electrical Engineering or Computer Engineering

Tools

Spyglass

Lint

CDC tools

Power analysis tools

Job description

**Role Overview**The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.**Key Responsibilities*** **Synthesis Ownership** + Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). + Develop and maintain synthesis scripts and flows for hierarchical and flat designs.* **Timing Closure** + Drive pre-layout and post-layout timing closure across multiple voltage and process corners. + Collaborate with STA teams to resolve setup/hold violations.* **Power & Area Optimization** + Apply physical-aware synthesis techniques to meet aggressive PPA targets. + Implement low-power strategies using UPF/CPF flows.* **Constraint Management** + Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.* **Cross-Functional Collaboration** + Work closely with RTL design, DFT, and physical design teams for seamless handoff. + Provide feedback to architecture and RTL teams for QoR improvements.* **Quality Checks** + Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.* **Flow Innovation** + Explore advanced synthesis methodologies and EDA tool capabilities for better QoR.* **Team Leadership** + Mentor junior engineers and drive best practices across synthesis and timing teams.**Minimum Qualifications:**• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.**Required Skills*** **Technical Expertise** + Strong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R. + Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).* **Low-Power Design** + Experience with UPF/CPF-based flows and multi-voltage designs.* **Scripting** + Advanced skills in Tcl, Perl, Python for automation.* **EDA Tools** + Familiarity with Spyglass, Lint, CDC tools, and power analysis tools.* **Leadership** + Ability to lead synthesis teams and coordinate with cross-functional groups.* **Education** + Bachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.* **Experience** + 15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.* **Preferred** + Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows. + Prior tape-out experience for NPU or DSP cores.**Applicants**: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.**To all Staffing and Recruiting Agencies**: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.If you would like more information about this role, please contact Qualcomm Careers.