NPU/AI Processor Synthesis (Design implementation) - Staff Engineer

QUALCOMM, Inc.; Hyderabad; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Qualcomm India Private Limited in Hyderabad is seeking a highly motivated Synthesis Engineer/Lead to join our NPU design team. You will own RTL-to-gate synthesis and timing closure for high‑performance AI/ML accelerators used in next-generation SoCs.

You will collaborate with Architecture, RTL Design, STA, DFT and Physical Design teams to deliver power-efficient silicon on advanced nodes, while developing flows, constraints, and automation to improve QoR, timing, and convergence.

Qualifications

• Bachelor’s or higher in EE/CE/CS with 4+ years hardware experience.
• Expertise RTL-to-GDS synthesis and timing closure on ASIC/LTE flow.
• Experience with low-power design methodologies and UPF flows.
• Proficiency in TCL; scripting in Python/Perl for flow automation.
• Strong collaboration with RTL, STA, DFT and Physical Design teams.

Responsibilities

• Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
• Develop and maintain synthesis flows, constraints, and automation.
• Drive pre-layout and post-layout timing closure across modes and corners.
• Optimize designs for PPA targets using physical-aware synthesis.
• Create and validate timing constraints (SDC) and clock definitions.
• Collaborate to resolve QoR, timing, power and convergence issues.
• Perform LEC, CDC, lint and low-power verification checks.

Skills

RTL synthesis

Timing closure

Constraint development

TCL scripting

Python/Perl scripting

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

PrimeTime

UPF-based low-power design

NPU/AI accelerator know-how

Clocking architecture

Education

B.E./B.Tech in EE/EC/CS

M.E./M.Tech or PhD (advantage)

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

PrimeTime

UPF-based flows

Job description

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:Job OverviewWe are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.Minimum Qualifications:• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.Key ResponsibilitiesOwn RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.Develop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.Drive pre-layout and post-layout timing closure across multiple modes and process corners.Optimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.Create, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.Collaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.Perform quality checks including LEC, CDC, lint, and low-power verification.Analyze and improve synthesis QoR through scripting and flow enhancements.Support tapeout activities and drive continuous improvements in synthesis methodologies.Required QualificationsBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.Strong understanding of ASIC design flow from RTL to GDS.Hands-on experience with RTL synthesis, timing closure, and constraint development.Expertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.Strong timing analysis knowledge using PrimeTime.Experience with low-power design methodologies and UPF-based flows.Good understanding of clocking architecture, timing constraints, and timing signoff.Proficiency in TCL and scripting languages such as Python or Perl.Excellent debugging, problem-solving, and cross-functional collaboration skills.Preferred QualificationsExperience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.Knowledge of advanced technology nodes (5nm, 4nm, 3nm and below).Experience with physical-aware synthesis and hierarchical design methodologies.Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.Proven track record of successful SoC or IP tapeouts.ExperienceSenior Engineer: 3-5 years of relevant experience.Lead Engineer: 5-8 years of relevant experience.Staff Engineer: 8-12 years of relevant experience.Sr Staff Engineer: 12-18 years of relevant experience.Principal Engineer: 18+ years of relevant experience.Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. 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