Lead RTL Design & Validation Engineer with DDR protocols exp

AMD; Hyderabad; On-site; INR 3,000,000 - 5,500,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD is seeking a senior engineer to design, implement, and validate firmware for DDR IP calibration. You will develop algorithms, run comprehensive validation, and collaborate with silicon, verification and system teams to ensure robust boot and memory training across DDR4/DDR5.

Role demands strong RTL/Verilog, embedded C, and experience with memory controller initialization, BP VPT considerations, and memory subsystems. Based in Hyderabad, India.

Qualifications

• DDR memory controller calibration solutions across DDR standards.
• Design and implement calibration firmware for DDR memory controllers.
• Develop and refine calibration algorithms for reliable memory initialization under PVT.
• Create validation plans and perform system bring-up and debugging for memory training.
• Collaborate with silicon design, verification and system engineering teams.
• Stay updated with emerging DDR technologies and calibration techniques.

Responsibilities

• Design and implement firmware for DDR memory controller calibration across DDR standards.
• Develop calibration algorithms to improve accuracy and convergence speed.
• Create and execute validation plans; perform bring-up and debugging for memory training.
• Align firmware with hardware capabilities; ensure integration across memory subsystem.
• Propose innovations to reduce boot time and support next-gen memory interfaces.

Skills

Verilog/SystemVerilog

C programming

Embedded systems

Team collaboration

Education

BE/BTech EE/CE

Tools

Perforce

Git

ICManage

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD's shapingthefuture.

Whetheryou're redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger- technologythat moves the world forward.Join us and, together, we'll advance your career.

THE ROLE:

The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD's DDR IPs and custom IPs.

THE PERSON:

Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions—including RTL logic, firmware routines, and algorithmic flows-into AMD's system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements. To work on custom IP projects.

KEY RESPONSIBILITIES:

• Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards
• Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines
• Create and execute validation plans to verify the correctness and performance of calibration firmware, algorithms and custom IPs. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability
• Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem
• Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces

PREFERRED EXPERIENCE:

• B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience
• Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges
• Circuit timing/STA, and practical experience with tools
• Working knowledge of C; embedded experience a plus
• Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards
• Been exposed to memory controller and PHYs from different IP vendors
• Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software
• Version control systems such as Perforce, ICManage or Git
• Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus
• Strong verbal and written communication skills
• Should have experience working in geographically dispersed team and should be a strong team player

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering with 12+ yrs of exp

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.