Lead I/O Design Engineer

NXP Semiconductors; Bengaluru; On-site; INR 900,000 - 1,400,000; Full time

Job summary

NXP Semiconductors in Bengaluru seeks an experienced IO Circuit Design Engineer with 5–8 years of expertise to design and validate high-performance IO circuits for advanced SoCs, including GPIO, LVDS, DDR, ESD protection, level shifters, and termination, using advanced CMOS technologies.

You will perform transistor-level design, SI analysis, layout reviews, silicon bring-up, and collaborate with cross-functional teams to deliver robust IO IP solutions.

Qualifications

• Bachelors or Masters in Electronics, Electrical, or Microelectronics.
• 5-8 years in analog/mixed-signal or IO circuit design.
• Experience with CMOS device physics and ESD design.
• Cadence Virtuoso hands-on required.
• Knowledge of LVS/DRC/EMIR checks.

Responsibilities

• Design and develop custom IO circuits including GPIO, LVDS, LVCMOS, DDR interfaces.
• Perform transistor-level design and simulation using CMOS technology nodes.
• Develop ESD protection circuits, level shifters, input buffers, output drivers, and on-chip termination.
• Conduct pre-layout and post-layout simulations for timing, power, noise, and reliability.
• Perform signal integrity analysis including IBIS model generation, package-aware simulations, crosstalk, and reflection analysis.
• Drive layout reviews and work with physical design teams to ensure quality.
• Support silicon bring-up, characterization, debugging, and production ramp activities.
• Collaborate with system, package, reliability, and product engineering teams.
• Develop and maintain design documentation, specifications, and verification reports.

Job description

Job Summary

We are seeking an experienced IO Circuit Design Engineer with 5-8 years of expertise in designing and validating high-performance I/O circuits for advanced semiconductor SoCs. The role involves developing GPIO, LVDS, DDR, SerDes support circuits, ESD protection, level shifters, buffers, and termination circuits using advanced CMOS technologies. The candidate will be responsible for transistor-level design, signal integrity analysis, layout reviews, silicon bring-up, and cross-functional collaboration to deliver robust, production-ready IO IP solutions. Strong hands-on experience with Cadence Virtuoso, SPICE simulation, ESD methodologies, and high-speed interface standards is essential.

Key Responsibilities

• Design and develop custom IO circuits including GPIO, LVDS, LVCMOS, SSTL, HSTL, DDR interfaces, and high-speed SerDes support circuits.
• Perform transistor-level design and simulation using advanced CMOS technology nodes.
• Develop and optimize ESD protection circuits, level shifters, input buffers, output drivers, and on-chip termination circuits.
• Conduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.
• Perform signal integrity analysis including IBIS model generation, package-aware simulations, crosstalk, and reflection analysis.
• Drive layout reviews and work closely with physical design teams to ensure design quality and performance targets.
• Support silicon bring-up, characterization, debugging, and production ramp activities.
• Collaborate with system, package, reliability, and product engineering teams.
• Develop and maintain design documentation, specifications, and verification reports.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
• 5-8 years of experience in Analog/Mixed-Signal or IO Circuit Design.
• Strong understanding of CMOS device physics, analog circuit design fundamentals, IO architectures and standards, and ESD design methodologies.
• Hands-on experience in custom circuit design using Cadence Virtuoso.
• Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.
• Experience with advanced technology nodes (16 nm/7 nm/5 nm preferred).
• Good knowledge of LVS, DRC, EMIR, and reliability checks.
• Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques.

Preferred Skills

• Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.
• Knowledge of package modeling and SI/PI analysis tools.
• Understanding of ESD standards such as HBM, CDM, and IEC.
• Experience in silicon validation and lab characterization.
• Scripting skills in Python, Perl, Tcl, or SKILL.
• Familiarity with IBIS and IBIS-AMI model generation.

Desired Competencies

• Strong analytical and debugging skills.
• Excellent communication and cross-functional collaboration.
• Ability to lead technical discussions and mentor junior engineers.
• Proven track record of delivering silicon successfully from specification to production.
• Self-driven with strong problem-solving abilities.
• Nice to have experience in automotive, AI/ML, networking, mobile, or data center SoCs.
• Exposure to functional safety and reliability requirements.
• Prior ownership of complete IO IP development cycle.

About NXP

More information about NXP in India... #LI-7013 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

For more information, visit www.nxp.com.

Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

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