Lead Engineer - CAD (Physical Verification ) - 6+years

Silicon Labs; Hyderabad; Presencial; INR 1.500.000 - 2.600.000; Tempo integral

Resumo da vaga

Silicon Labs in Hyderabad is seeking an experienced CAD PV engineer to support design and layout teams by debugging PV issues during the chip development cycle and by developing and QAing DRC, Antenna, Dummy fill and other rule decks. You will collaborate with CAD, ESD, Design, Layout, Packaging and foundry teams to gather requirements, perform impact analyses, lead deck reviews, and maintain PV flows.

Proficiency with Calibre SVRF, PVS, Pegasus, Calibre RVE/DRV and scripting in Perl/Python is

Qualificações

• 6+ years of related professional experience.
• Bachelor’s or Master’s degree in electrical engineering.
• Proficiency in developing and supporting DRC rule decks including custom rules in Calibre SVRF or similar languages.
• Experience in LVS, extraction and PERC rule decks is a plus.
• Experience working with design/layout engineers to debug PV issues.
• Proficiency in scripting languages like PERL, Python or Shell.
• Excellent communication and cross-team collaboration.

Responsabilidades

• Support design and layout teams to resolve PV issues during the design cycle.
• Develop and QA PV rule decks (DRC, Dummy fill, Antenna, and custom decks).
• Lead deck impact analysis meetings with stakeholders.
• Collaborate with CAD, ESD, Design, Layout, Packaging and foundry teams to gather deck requirements.
• Conduct code reviews and create QA tests for decks.
• Develop and maintain PV flows and methodologies to improve quality.
• Evaluate new tools and features and benchmark them.
• Work with external vendors to report and track bugs.

Conhecimentos

PV debugging

Deck development

Cross-functional collaboration

Scripting (Perl/Python/Shell)

Communication

Formação

Bachelor’s or Master’s in Electrical Engineering

Ferramentas

Calibre SVRF

PVS

Pegasus

Calibre RVE

Calibre DRV

Virtuoso

LVS/Extraction/PERC tooling

Perl

Python

Descrição da vaga

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Meet the Team

As part of central CAD group, CAD Physical Verification (PV) team is responsible for supporting design and layout teams during chip development by debugging PV related queries, developing and supporting various PV decks like DRC, Antenna, Dummy fill, LVS and extraction.In addition, the team collaborates and collects specs from other teams to code decks like PERC, Float, Density, XOR from scratch. The team is also responsible for developing and automating various flows and methodologies to improve verification quality and optimize performance.

Responsibilities

• Support design and layout teams to resolve any PV related issues during design development cycle
• Development and QA of various physical verification rule decks like DRC, Dummy fill, Antenna and other custom decks
• Conduct and drive impact analysis meetings with stakeholders for deck updates
• Collaborate closely with CAD, ESD, Design, Layout, Packaging and foundry teams to obtain requirements for deck development.
• Conduct code reviews and create custom QA testcases to validate the quality of rule decks.
• Develop and maintain PV flows and methodologies to improve quality and performance
• Perform new tool/feature evaluations and benchmarks.
• Work closely with external vendors to report and track bugs in the software

Skills you’ll need:

• 6+ years of related professional experience
• Bachelor’s or Master’s degree in electrical engineering
• Proficiency in developing and supporting DRC rule decks including custom rules in Calibre SVRF or similar languages
• Experience in coding LVS, extraction and PERC rule decks is a plus
• Experience working with design/layout engineers in debugging PV issues.
• Knowledge of using physical verification tools like PVS, Pegasus, Calibre RVE, Calibre DRV, Virtuoso layout editor etc
• Proficiency in scripting languages like PERL/Python/Shell for developing custom scripts
• Excellent communication skills and experience in collaborating with different teams for collecting initial specs, deck development, support and leading deck impact analysis meetings.
• Ability to work independently, drive decision-making, detail oriented and documentation skills are critical.

At Silicon Labs, you’ll be part of a highly skilled team where every engineer makes a meaningful impact. We promote work-life balance and a welcoming, fun environment.