Lead DFT Engineer (Scan Insertion | ATPG | MBIST )

Advanced Micro Devices, Inc; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD in Bengaluru, India, seeks a highly experienced DFT/ASIC engineer to implement and verify DFT architectures, including scan insertion and ATPG pattern generation. You will work with senior silicon design engineers to achieve first pass silicon success and provide post-silicon support for yield learning.

The candidate should have 12+ years of experience and a strong background in DFT methodologies (IEEE1500, JTAG 1149.x), Verilog RTL, and scripting with Perl/Shell.

Qualifications

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
• 12+ years of experience in the field.

Responsibilities

• Implementation and verification of DFT architecture and features.
• Scan insertion and ATPG pattern generation.
• ATPG patterns verification with gate-level simulation.
• Test coverage and test cost reduction analysis.
• Post-silicon support to ensure successful bring-up and yield learning.

Skills

DFT verification

JTAG 1149.x

IEEE1500

Scan

ATPG

Verilog RTL

Perl scripting

Shell scripting

VCS simulation

Education

Bachelor's or Master's in computer engineering/Electrical Engineering

Tools

Mentor Testkompress

Synopsys Tetramax/DFTMAX

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Implementation and verification of DFT architecture and features

• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.).
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering with 12+ Years of exp.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.