Lead DFT Engineer (Scan Insertion | ATPG | MBIST )

Advanced Micro Devices, Inc.; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

Advanced Micro Devices, Inc. in Bengaluru seeks a senior DFT Design Engineer to help bring first-pass silicon to life. You will work with front-end design/integration teams to implement and verify DFT architectures, scan insertion, and ATPG patterns with gate-level simulation.

You should be highly accurate, with strong communication and problem‑solving skills, and possess extensive experience in DFT methodologies, EDA tools, and Verilog RTL design.

Qualifications

• Bachelors or Masters in computer engineering or electrical engineering with 12+ years of experience.
• Strong knowledge of DFT architectures and verification.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis; post silicon support to ensure successful bring up and yield learning

Skills

DFT verification methods

IEEE1500

JTAG 1149.x

Scan insertion

ATPG pattern generation

Gate-level simulation

Verilog RTL design

VCS

Perl/Shell scripting

Education

Bachelor's or Master's in Computer Engineering or Electrical Engineering

Tools

Mentor TestKompress

Synopsys Tetramax/DFTMAX

ModelSim/VCS

Verilog

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

The Person

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

Key Responsiblities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysisPost silicon support to ensure successful bring up and enhance yield learning

Preferred Experience

• Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering with 12+ Years of exp.

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

This posting is for an existing vacancy.