IP/Subsystem Verification Lead

AMD; Bengaluru; On-site; INR 2,500,000 - 3,000,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD is looking for an MTS Silicon Design Engineer in Bengaluru, Karnataka. You'll play a key role in bringing FPGA and ASIC products to life through verification. This position emphasizes collaboration with architects and engineers while developing UVM-based testbenches and ensuring design functionality and performance.

A successful candidate will have extensive experience in ASIC verification and strong communication skills. Your work will contribute significantly to next-generation computing experiences at AMD.

Qualifications

• 8–10 years of experience in ASIC verification.
• Proficient in IP-level ASIC verification.
• Experience scripting and automating verification processes.

Responsibilities

• Collaborate with architects, hardware, and firmware engineers.
• Code system-level UVM-based testbenches and verification components.
• Run regressions and debug test failures for quality assurance.

Skills

Experience with PCIe

SystemVerilog

Analytical skills

Communication skills

Leadership or mentorship

Education

Bachelor’s or Master’s degree in computer engineering or electrical engineering

Tools

UVM-based verification frameworks

Python

Verilog

Job description

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

MTS Silicon Design Engineer

As an IP verification engineer in the AECG Group, you will help bring to life cutting‑edge FPGA and ASIC products for a variety of target customers. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first‑pass silicon success.

The Person

You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player with excellent communication skills and experience collaborating with engineers located in different sites/time zones. You possess strong analytical and problem‑solving skills, are willing to learn, and ready to take on challenges.

Key Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe, CXL, and related IPs.
• Develop test plan documentation, accounting for interactions with other features, hardware, firmware, and software driver use cases.
• Code IP or system‑level UVM‑based testbenches and verification components—monitors, scoreboards, checkers.
• Build directed and random verification tests.
• Run regressions, debug test failures to ensure high design functionality, performance, and implementation quality.

Preferred Experience

• 8–10 years of experience in ASIC verification.
• Experience with PCIe, CXL, or Ethernet protocols.
• Proficient in IP‑level ASIC verification.
• Expertise in Verilog, SystemVerilog, and object‑oriented programming.
• Expertise in developing UVM‑based verification frameworks and testbenches.
• Experience scripting and automating verification processes and flows.
• Experience with leadership or mentorship is an asset.
• Experience working in a team environment through the ASIC/FPGA project lifecycle from planning to tape‑out.
• Exposure to simulation profiling, efficiency improvement, acceleration, HLS tools/processes.
• Comfortable in Python, Perl, and editing/maintaining scripts.
• Strong communication skills and ability to work independently as well as in a cross‑site team environment.
• Good knowledge of computer architecture and systems is a plus.
• Exposure to generative AI or simulation tools for test, testbench, assertion, test‑plan generation, or performance optimization is a plus.

Academic Credentials

• Bachelor’s or Master’s degree in computer engineering or electrical engineering.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.