Intel Hiring For SOC Design Engineer at Bengaluru / Bangalore

Intel; Bengaluru; On-site; INR 12,00,000 - 24,00,000; Full time

Job summary

Join a leading technology firm as a Structural and Physical Design Engineer in a dynamic team focused on cutting-edge Ethernet technology. This role offers the opportunity to work on advanced process nodes, driving the physical design of Ethernet Network Interface Controllers and SOCs. With a strong emphasis on collaboration and innovation, you'll tackle complex challenges from RTL synthesis through to final sign-off. If you're passionate about microelectronics and eager to contribute to impactful projects in a multicultural environment, this position is a perfect fit for you. Embrace the chance to advance your career in a pivotal role at a global leader in technology.

Qualifications

• 10+ years of experience in physical design with a strong track record of successful chip tape-outs.
• Hands-on expertise with EDA tools and backend challenges on advanced process nodes.

Responsibilities

• Responsible for end-to-end physical implementation of blocks from RTL synthesis to sign-off.
• Manage physical design tasks including floorplanning, clock tree synthesis, and timing closure.

Skills

Physical Design

RTL Synthesis

Static Timing Analysis

Low Power Design Methodology

EDA Tools (Synopsys ICC2, Cadence Innovus)

Chip Level Layout Verification

Communication Skills

Team Collaboration

Education

Bachelor's in Electrical Engineering

Master's in Electronics Engineering

Tools

Synopsys ICC2

Cadence Innovus

PrimeTime

RedHawk

Calibre

Job description

Job Description
Silicon Engineering of Intel’s Ethernet Product Group is looking for Structural and Physical Design engineers to build Ethernet Network Interface Controller IP and SOCs. The selected candidate will be joining its India team and work on IP/subsystem/full chip level physical design tasks spanning from RTL synthesis to final sign-off. The role in question is for a block level physical design engineer who would be responsible for end-to-end physical implementation of one or more blocks starting from RTL synthesis, floorplanning, clock tree synthesis, timing and physical convergence.

Qualifications

1. Solid track record of taping out multiple chips on advanced process technology nodes such as 7nm, 10nm.
2. Hands-on experience with industry standard EDA tools such as Synopsys ICC2, Fusion Compiler, and/or Cadence Innovus along with PrimeTime, RedHawk, and Calibre is mandatory.
3. Thorough technical understanding of backend challenges such as place and route on advanced process nodes, Static Timing Analysis for high frequency designs, impact of EM/IR/ESD on yield and manufacturability, low power design methodology and verification.
4. Candidate should have handled chip level layout verification tasks for more than 1 project.
5. Good grip on physical sign-off strategies and design for manufacturability concepts.
6. Good communication skills to thrive in a multicultural environment and manage ambiguity and schedule challenges.
7. Must be a team player.
8. Bachelors/Masters in Electrical (EE)/Electronics (EC) Engineering with specialization in Microelectronics/VLSI Design and/or related domains along with a minimum relevant industry experience of 10+ years.

Inside this Business Group
The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. Its leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.