HP DSP core Implementation (Synthesis) Senior Lead Engineer

QUALCOMM, Inc.; Dadri; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

QUALCOMM, Inc. in Dadri, Uttar Pradesh invites an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP development for high performance, low power products.

You will collaborate with cross-functional teams to determine the product execution path. Requirements include 3+ years in ASIC design/verification (or 2+ years with a Master's, or 1+ year with a PhD) and hands-on experience in synthesis, timing constraints, and power

Qualifications

• Bachelor's degree in Science/Engineering with 3+ years ASIC design/verification experience.
• Master's degree in Science/Engineering with 2+ years ASIC design/verification experience.
• PhD in Science/Engineering with 1+ year ASIC design/verification experience.

Responsibilities

• Strong understanding of Physical Synthesis and Synthesis methodologies with industry standard tools.
• Write timing constraints for synthesis, STA, timing closure and pipelining for performance optimization.
• Handle timing closure for multi-clock domain designs.
• Familiar with MCMM synthesis and optimization.
• Understand low-power design implementation using UPF.
• Experience with Perl/Python and TCL scripting.
• Experience with clock gating and other power optimization techniques.
• Collaborate with design, DFT and PD teams for netlist delivery and timing constraints validation.
• Handle ECOs and formal verification and maintain high-quality matrix.

Skills

Python

Tcl

Verilog

VHDL

QoR optimization

Version control

Configuration management

Regression

Scripting

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Fusion Compiler

Genus

LEC signoff tools

Synthesis

Job description

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Experience

5 to 8 years of hands on experience in Synthesis and LEC

Job Role

• Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
• Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
• Experience in all aspects of timing closure for multi-clock domain designs.
• Should be familiar with MCMM synthesis and optimization.
• Should have good understanding of low-power design implementation using UPF.
• Experience with scripting language such as Perl/ Python, TCL.
• Experience with different power optimization flows or technique such as clock gating.
• Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
• Should be able to handle ECOs and formal verification and maintain high quality matrix

Skill Set

• Proficiency in Python/Tcl
• Familiar with Synthesis tools (Fusion Compiler/Genus)
• Fair knowledge in LEC, LP signoff tools
• Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization Equivalence Checking
• Familiarity with standard software engineering practices like Version
• Control, Configuration Management, Regression is a plus
• Should be sincere, dedicated and willing to take up new challenges