Hardware Engineer III

Tower Research Capital; Gurugram District; Hybrid; INR 2,400,000 - 4,200,000; Full time

Benefits offered by this job

Hybrid working opportunities

Free breakfast, lunch and snacks

In-office wellness reimbursements

Volunteer opportunities

Social events and learning workshops

Job summary

Tower Research Capital is hiring in Gurugram to build world-class low-latency trading infrastructure. You will contribute to FPGA/ASIC development, design interfaces, and optimize data paths for exchange connectivity, collaborating across global teams and time zones.

The role emphasizes Verilog/SystemVerilog/VHDL expertise, C/C++ software interaction, and Linux-based verification in a dynamic, hybrid work setting.

Qualifications

• Bachelor's degree in electrical engineering or equivalent with 3–5 years in ASIC/FPGA development.
• Expertise with FPGA/ASIC development using Verilog, SystemVerilog and/or VHDL and FPGA design flows.
• Experience with hardware verification methods and tools and Linux environments.

Responsibilities

• Collaborate with software developers to architect low-latency connections to exchanges.
• Develop FPGA/ASIC hardware interfaces and signal processing cores.
• Integrate network stacks and optimize data parsing for user space.
• Work with global teams across time zones on FPGA kernel driver development.
• Design and verify high-speed networking systems (PCIe, Ethernet) and related hardware.

Skills

FPGA development

ASIC development

Verilog/SystemVerilog/VHDL

C/C++ programming

Python scripting

Education

Bachelor's degree in Electrical Engineering

Tools

Xilinx tools

cocotb

UVM

Formal verification

Job description

Tower is home to some of the world’s best systematic trading and engineering talent. We empower portfolio managers to build their teams and strategies independently while providing the economies of scale that come from a large, global organization.

Engineers thrive at Tower while developing electronic trading infrastructure at a world class level. Our engineers solve challenging problems in the realms of low-latency programming, FPGA technology, hardware acceleration and machine learning. Our ongoing investment in top engineering talent and technology ensures our platform remains unmatched in terms of functionality, scalability and performance.

At Tower, every employee plays a role in our success. Our Business Support teams are essential to building and maintaining the platform that powers everything we do — combining market access, data, compute, and research infrastructure with risk management, compliance, and a full suite of business services. Our Business Support teams enable our trading and engineering teams to perform at their best.

At Tower, employees will find a stimulating, results-oriented environment where highly intelligent and motivated colleagues inspire each other to reach their greatest potential.

Responsibilities

• Collaborating with software developers across divisions to architect low-latency connections to financial exchanges around the world
• Building advanced Ethernet-based communication stacks direct from chip to SFP
• Integrating network stacks to connect to various financial exchanges
• Creating custom logic to manage a constant inflow of data, which will need to be parsed, processed, and passed to the user space in the most efficient manner possible
• Working closely with software developers to develop an optimal interface between FPGA hardware and user space software

Qualifications

• A bachelor’s degree in electrical engineering or a related field, or equivalent professional experience, with at least 3–5 years of experience in ASIC and/or FPGA development; verification experience is required.
• Expertise in FPGA and ASIC development using Verilog, SystemVerilog, and/or VHDL, including FPGA design flows (synthesis, place and route, and static timing analysis), Xilinx FPGA products and development tools, and industry-standard simulators.
• Experience with hardware verification methodologies and tools, including cocotb, UVM, and formal verification; Ethernet protocols, PCIe, switching and routing, traffic parsing and shaping, network PHY interfacing, third-party IP/core integration, Linux environments, shell scripting, Python or similar scripting languages, and documenting design and interface specifications.
• The ability to design and develop FPGA-based signal processing cores from system and architectural requirements, with experience collaborating across global teams and time zones.
• A background in high-speed networking technologies, including 100 Mbps, 1 Gbps, 10 Gbps, and 40 Gbps network interfaces, and an understanding of network hardware techniques such as store-and-forward; previous experience in a high-frequency trading environment is preferred.
• Experience with FPGA kernel driver development and C/C++ programming, along with a strong mathematical foundation, analytical and problem-solving abilities, and strong communication and collaboration skills.

Benefits

• Generous paid time off policies
• Savings plans and other financial wellness tools available in each region
• Hybrid working opportunities
• Free breakfast, lunch, and snacks daily
• In-office wellness experiences and reimbursement for select wellness expenses (e.g., gym, personal training and more)
• Company-sponsored sports teams and fitness events (JPM Corporate Challenge, Cycle for Survival, Wall Street Rides FAR and more)
• Volunteer opportunities and charitable giving
• Social events, happy hours, treats, and celebrations throughout the year
• Workshops and continuous learning opportunities

At Tower, you’ll find a collaborative and welcoming culture, a diverse team and a workplace that values both performance and enjoyment. No unnecessary hierarchy. No ego. Just great people doing great work – together.

Tower Research Capital is an equal opportunity employer.