Full chip Physical verification Engineer

AMD; Hyderabad; On-site; INR 1,500,000 - 2,100,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD in Hyderabad, India, invites experienced engineers to lead full chip integration and physical verification for FPGA/SOC designs. The role emphasizes automation of integration activities to minimize human error and improve team efficiency, working with CAD and EDA vendors to streamline tapeouts on 7nm and smaller nodes.

The candidate should have 9+ years in FPGA/SOC verification, PDK updates, and RDL/Ubump development, with strong scripting in Perl/Tcl and Python.

Qualifications

• 9+ years of FPGA/SOC full chip physical verification experience
• Experience with PDK updates, RDL/Bump/Ubump development
• Strong automation mindset to reduce human error in integration flows
• Knowledge of 7nm and smaller nodes and related CAD/EDA tools

Responsibilities

• SOC RDL development for monolithic and advanced package technologies
• Full chip integration and physical verification of FPGA/SOC designs
• Collaborate with PD, CAD, SiTech, EMIR, PKG and EDA vendors for IP integration and on-time tapeout
• Automate integration flows to improve functional efficiency
• Debug LVS/DRC/Antenna issues with multi-point approaches and rule-file customization

Skills

Scripting (Perl)

Scripting ( Tcl )

Python basics

FPGA/SOC verification

Education

Bachelor's or Master's in Electrical/Electrical Engineering

Tools

SKILL

PERL

TCL

Python

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbring leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

The focus of this role is to lead full chip integration and phsyical verification activities. To actively work on automation of the integration activities thus reducing the human error. Improve the overall efficiency of the team by innovating and executing with leading EDA features.

THE PERSON:

Master’s/Bachelor’s Degree in Electrical/Electronic engineering with 9+ years of experience in FPGA/SOC full chip physical verification, PDK updates, RDL/Bump/Ubump development is required. Strong scripting skills in PERL/TCL/Phython is must.

Successful candidate would be responsible for full chip integration and physical verification of 7nm and lower nodes. You will be actively working with CAD and EDA vendors to improve and automate the integration flows thus by improving the overall fucntional efficiency. Thisjobrequires excellent teamwork, great communication and strong problem-solving skill.

KEY RESPONSIBILITIES:

• SOC RDL development for monolethic and Advanced package technologies.
• Full chip integration and physical verification of FPGA/SOC designs
• Work closely with PD, CAD, SiTech, EMIR, PKG and EDA vendors for seamless integration of IPs into full chip for ontime tapeout.
• Actively work on automation of integration flows to improve the functional efficiency.
• Debug the full chip LVS/DRC/Antenna issues with multi point approach and ability to modify the rule files for quicker debug

PREFERRED EXPERIENCE:

• Experience in bump & ubump RDL development and 3D integration of AoA or SSIT designs will be desirable.
• Should be well versed with FinFet technology DRC debugging and fixes.
• Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks.
• Knowledge of scripting languages like SKILL, PERL, TCL etc. is must.
• Strong problem solving skills and excellent communication skills.
• Sound knowledge of hierarchical layout handling including macros and full chip.
• Knowledge in PDK (DRC/LVS rule files) is preferred.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s "Responsible AI Policy" is available here.

This posting is for an existing vacancy.