FPGA Silicon Design Verification Engineer

Altera Digital Health; Bengaluru; On-site; INR 8,00,000 - 12,00,000; Full time

Job summary

A leading digital health technology company is seeking a verification engineer to design effective testbench and verification strategies. The ideal candidate will have at least 5 years of experience in verification engineering, with a strong background in SystemVerilog and UVM methodology. This role offers the opportunity to work with cutting-edge technologies in a collaborative environment in Bengaluru, India.

Qualifications

• Minimum of 5 years of experience in verification engineering.
• Experience with building UVM infrastructure.
• Experience with functional and code coverage.

Responsibilities

• Architect effective testbench and verification strategies.
• Produce functional coverage and code coverage.
• Analyze root causes and develop constrained random stimulus.

Skills

SystemVerilog

UVM methodology

Scripting (Perl/Python)

Education

Bachelor's Degree in Electrical Engineering or related field

Tools

C/C++ models

RTL simulators

Job description

Overview

As a verification engineer you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.

Qualifications

Minimum Qualifications:

• Bachelors Degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum of 5Y of experience in the following:
• Experience with SystemVerilog.
• Experience with UVM or OVM methodology.
• Experience with scripting perl/Python

Preferred Qualifications:

• Masters Degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with using C/C++ models as golden models to compare with RTL.
• Experience with code coverage.
• Experience with functional coverage.
• Experience with X-propagation.
• Experience with multiple RTL simulators.
• Experience with regression testing.
• Experience creating components that are reusable from block to top.
• Experience in Ethernet/PCIE/AXI/DDR protocols is an added advantage.