FPGA Engineer

Digantara; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Benefits offered by this job

Competitive incentives

Galvanizing team

Space tech project

Job summary

Digantara is seeking an FPGA design Engineer to design RTL modules for satellite payload electronics and ensure on-board processing capabilities. You will implement high-speed interfaces and integrate IP blocks for Xilinx/Microchip devices, aligning with the overall payload architecture.

The ideal candidate has 4–6 years of RTL design experience, proficiency in VHDL/Verilog, and hands-on use of Vivado/Libero.

Qualifications

• B.Tech/B.E in Electronics Engineering or M.Tech/M.E or PhD in Microelectronics/Embedded systems/VLSI.
• 4 to 6 years RTL design experience for FPGA-based digital systems.
• Proficient in VHDL/Verilog and FPGA design flow using Vivado/Libero.
• Deep understanding of Synthesis, STA, clock domain crossing, timing closure.
• Proficient with FPGA/SoC development kits and electronic test equipment.

Responsibilities

• Design and develop high-performance RTL modules for the FPGA-based payload electronics, to accomplish on-board processing requirements.
• Develop high quality RTL and efficient custom IP blocks in VHDL/Verilog for AMD-Xilinx/Microchip FPGA target devices.
• Implement high-speed interfaces such as SerDes, Gigabit Ethernet, PCIe, and AXI-4/AXI-4 Lite interface with processor.
• Carry out Synthesis, Place and Route, STA and close timing requirements of the FPGA design.
• Collaborate with hardware, embedded software and algorithm processing engineers to generate RTL design requirements, architecture and test plans.
• Document the FPGA design, verification and validation, board level test results throughout the development lifecycle.

Skills

RTL design

Verilog/VHDL

FPGA design flow

Synthesis/STA

Timing closure

Troubleshooting

FPGA kits

Education

B.Tech/B.E Electronics

M.Tech/M.E Microelectronics/Embedded systems/VLSI

PhD in Microelectronics/Embedded systems/VLSI

Tools

Vivado

Libero EDA

Questasim

Job description

Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception (data collection), comprehension (data processing), and prediction (analytics). This holistic approach empowers Digantara to monitor all Resident Space Objects (RSOs) in orbit, fostering comprehensive domain awareness.

Digantara is seeking an FPGA design Engineer to design and develop RTL modules for satellite payload electronics. The engineer will be responsible for implementing various algorithms and suitable data, control interfaces between payload & satellite bus.

Why Us?

• Competitive incentives, galvanizing workspace, blazing team, frequent outings—pretty much everything you have heard about a startup + you get to work on space technology.
• Hustle in a well-funded startup allowing you to take charge of your responsibilities and create your moonshot.

Ideal Candidate

Someone with expertise in FPGA design for the satellite payload electronics/ground-based systems.

Responsibilities

• Design and develop high-performance RTL modules for the FPGA based payload electronics, to accomplish on-board processing requirements.
• Develop high quality RTL and efficient custom IP blocks in VHDL/Verilog for AMD-Xilinx/Microchip FPGA target devices.
• Implement high-speed interfaces such as SerDes, Gigabit ethernet, PCIe, and AXI-4/AXI-4 Lite interface with processor.
• Carryout Synthesis, Place and Route, static timing analysis (STA) and close the timing requirements of the FPGA design.
• Collaborate with hardware, embedded software and algorithm processing engineers to generate RTL design requirements, architecture and test plans.
• Document the FPGA design, verification and validation, board level test results throughout the development lifecycle.

Required Qualifications

• B.Tech/B.E in Electronics Engineering or M.Tech/M.E or PhD degree Microelectronics/Embedded systems/VLSI.
• 4 to 6 years of demonstrated experience in RTL design and development for FPGA based digital systems.
• Strong proficiency in VHDL/Verilog based digital logic implementation with expertise in FPGA design flow using Vivado/Libero EDA tools.
• Deep understanding of FPGA architecture, Synthesis and Static Timing Analysis, Clock domain crossing techniques, and timing closure.
• Strong expertise in troubleshooting logical and timing observations during development lifecycle.
• Proficiency in working with FPGA/SoC development kits and electronic test equipment.

Preferred Skills

• Experience in developing reliable and robust FPGA designs for satellite payloads is a significant plus.
• Experience with Questasim or similar tools for functional verification and code coverage analysis.
• Knowledge of Embedded software development in C/C++ and algorithm implementation in MATLAB/Python.
• Knowledge of the latest advancements in FPGA based payload electronics development.
• Familiarity with the standards for satellite hardware development is an advantage.

General Requirements

• Ability to work in a mission-focused, operational environment.
• Ability to think critically and make independent decisions.
• Interpersonal skills to enable working in a diverse and dynamic team.
• Maintain a regular and predictable work schedule.
• Writing and delivering technical documents and briefings.
• Verbal and written communications skills as well as organizational skills.
• Travel occasionally as necessary.

Job Location:

Hebbal, Bengaluru.

Work Type:

WFO with alternate Saturdays.