Engineer II - CAD

Microchip Technology Inc.; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Microchip Technology Inc. in Bengaluru, India invites a skilled CAD engineer to join the EDA/ASIC team. You will contribute to the RTL-to-GDS design flow, automate toolchains with TCL/Python, and optimize timing closure across multi-node projects.

Collaborate with global business units and vendor partners to test new features, validate constraints, and improve PPA. A strong background in EDA tools and IC design is essential for success.

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics/ECE/CS/VLSI required.
• 2–8 years of relevant experience; travel 0–25%.
• Strong scripting in TCL/Python and flow automation.
• Experience with RTL2GDS timing closure and logic synthesis.

Responsibilities

• Support ASIC design flows from RTL to GDS and automate CAD tool flows.
• Collaborate with global business units to tailor CAD solutions.
• Test and validate new EDA features with vendors; optimize PPA.
• Ensure design constraints (SDC) are implemented across modes.

Skills

RTL to GDS flow

Tcl/Python scripting

EDA tool automation

AI-driven EDA awareness

Education

BE/B.Tech / M.E./M.Tech (Electronics/ECE/CS/VLSI)

Tools

Synopsys Fusion Compiler

Synopsys DC

Cadence Genus

Cadence Tempus

Cadence Innovus

Formal verification tools

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!

Job Description

The CAD group at Microchip offers global support for technologies and tools used in product development providing innovative solutions for the design community.

A successful candidate in this role will participate in various aspects of EDA support and developing next-generation ASIC design flow and methodology.

He / She will also work closely with various business units across the globe to understand their needs and foster innovative ideas to solve complex problems.

Key Requirement

Good Knowledge of design flows from RTL design through synthesis, formal verification, and timing closure for RTL2GDS delivery. undefined Design, benchmark, and deploy automated CAD tool flows focusing on logic synthesis, hierarchical optimization, physical synthesis, and chip sign-off timing.

Automation & Tools Customization: Write and optimize highly robust, scalable scripts using Tcl and Python to reduce Flow Turnaround Time (TAT) and build automated tracking tools for timing data.

Synthesis & Equivalence Verification: Build and optimize front-end flows utilizing advanced tools for logical/physical synthesis and Formal Verification/Logic Equivalence Checking (LEC).

Hands-on experience with one or more of the following industry-standard toolsets: Synopsys Fusion Compiler, DC, PrimeTime Cadence Genus, Tempus or Innovus Exposure to leveraging AI driven EDA capabilities (e.g., Synopsys FC.ai, Cadence Cerebrus) to automate PPA exploration and timing closure optimization.

Standardize and automate the validation of Synopsys Design Constraints (SDC) across all functional and test modes.

Partner directly with major EDA vendors to test next-generation features, troubleshoot internal tool failures, and adapt flows for deep sub-micron advanced process nodes.

Excellent verbal and written communication skills.

Requirements/Qualifications

B.E./B.TECH/M.E./M TECH (Electronics/ECE/CS/VLSI). 2 to 8 Years of relevant experience is required Travel Time: 0% - 25%

To all recruitment agencies

Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

At Microchip, employees are our greatest strength. As one of the top performing semiconductor companies in the world, we are led by a set of guiding values and a mission to empower innovation to enhance the human experience. We work tirelessly to create a company culture that highlights how important every employee is to our mission.

Microchip Recruitment Privacy Notice Recruitment Scam Alert

Microchip will never: Request banking or payment information during the application or interview process. Ask candidates to register or pay for a training class as part of the application or interview process. Ask candidates to receive or ship packages or goods as part of the recruitment process. Use email address not ending with "@microchip.com". Use instant messaging to communicate. Be wary of generic emails or vague job details. If something feels suspicious, stop communicating immediately. To report potential scams, contact us at [e-mail].