Director, Logical Design

Graphcore; Bengaluru; On-site; INR 6,000,000 - 10,000,000; Full time

Job summary

Graphcore is seeking an experienced engineering leader to drive the design and development of complex, high-performance SoCs for next-generation AI acceleration platforms. You will guide technical decisions, build high-performing teams and deliver silicon solutions with a strong emphasis on power, area and performance.

The role requires deep expertise in ASIC/SoC design, RTL development and leadership across distributed teams, including tapeouts, with collaboration across architecture,

Qualifications

• 18+ years of experience in ASIC/SoC design and engineering leadership.
• Proven track record delivering multiple complex SoC tapeouts.
• Strong expertise in digital design, microarchitecture and RTL development.
• Deep knowledge of Verilog/SystemVerilog and clock/reset architectures.
• Experience with high-speed interfaces (PCIe, DDR, Ethernet).
• Ability to manage risks, schedules, and cross-functional dependencies.
• Excellent communication and stakeholder management across distributed teams.

Responsibilities

• Provide technical leadership for microarchitecture, RTL design and SoC integration.
• Drive delivery of complex SoC designs to tapeout milestones.
• Collaborate with architecture, verification, DFT and physical design teams.
• Identify and mitigate technical risks and resource needs.
• Build and develop a high-performing engineering team.
• Drive process improvements and design automation initiatives.
• Represent the team in technical reviews and cross-functional discussions.

Skills

SoC design leadership

RTL design

Microarchitecture

Verilog/SystemVerilog

Engineering management

Team leadership

Cross-functional collaboration

Project planning

Risk management

Communication skills

Education

Electronic Engineering / Computer Science degree

Tools

EDA tools

Synthesis tools

Timing analysis tools

Job description

Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI's rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference.

We are looking for an experienced engineering leader to drive the design and development of complex, high-performance SoCs for next-generation AI acceleration platforms.

The role combines strong technical expertise with people leadership and engineering execution, requiring the ability to guide technical decisions, build high-performing teams and deliver high-quality silicon solutions.

The Team

The SoC Design team is responsible for the RTL design, development and integration of critical subsystems within Graphcore's AI acceleration platforms.

The team works closely with architecture, verification, DFT and physical design teams throughout the silicon development lifecycle, from microarchitecture through implementation and sign-off.

Responsibilities and Duties

• Provide technical leadership for microarchitecture, RTL design and SoC integration, driving design decisions and trade-offs across functionality, performance, power and area.
• Lead engineering execution and delivery of complex SoC designs, ensuring alignment with project milestones, quality objectives and tapeout schedules.
• Drive design quality and implementation readiness, including CDC/RDC, synthesis, timing closure and physical implementation considerations.
• Collaborate with architecture, verification, DFT and physical design teams to resolve complex technical challenges and ensure successful silicon delivery.
• Identify and manage technical risks, resource requirements and cross-functional dependencies to ensure effective project execution.
• Build, lead and develop a high-performing engineering team through coaching, mentoring, performance management and talent development.
• Drive continuous improvement in design methodologies, engineering processes and team productivity.
• Represent the design team in technical reviews, project planning and cross-functional discussions, ensuring alignment with broader engineering objectives.

Candidate Profile

• Degree in Electronic Engineering, Computer Science or a related discipline with 18+ Years of experience
• Extensive experience in ASIC/SoC design and development, including technical leadership and engineering management.
• Proven experience leading engineering teams through multiple complex SoC tapeouts, with end-to-end ownership of design execution and delivery.
• Strong expertise in digital design, microarchitecture, RTL development and complex SoC integration.
• In-depth knowledge of Verilog/SystemVerilog, SoC interconnect protocols and clock/reset architectures.
• Good understanding of synthesis, static timing analysis, CDC/RDC, low-power design and physical implementation considerations.
• Demonstrated ability to manage technical risks, schedules, resources and cross-functional dependencies across complex silicon development programs.
• Proven experience in building, managing and developing high-performing engineering teams.
• Strong technical judgement, problem-solving and decision-making skills.
• Excellent communication, stakeholder management and collaboration skills, with experience working across globally distributed teams.
• Experience in high-performance, multicore or AI accelerator SoC development.
• Experience with advanced process technologies and physically aware RTL design.
• Knowledge of DFT methodologies, low-power design and multi-voltage domain integration.
• Experience with multi-die or chiplet-based SoC architectures.
• Knowledge of high-speed interfaces such as PCIe, DDR and Ethernet.
• Experience in silicon bring-up, post-silicon debugging and ECO implementation.

Experience driving engineering methodology improvements and design automation