Director , Engineering (GPU Physical Design)

QUALCOMM, Inc.; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru seeks an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP development for high‑performance, low‑power products. You will collaborate with cross‑functional teams to determine the best execution path.

Requires Bachelor's/Master’s/PhD in Electrical/Electronic Engineering with 20+ years Physical Design experience and 10 years leading a team on high‑performance cores; strong

Qualifications

• Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution
• 20+ years of experience in Physical Design/Implementation
• 10 years of experience in leading a team working on high performance cores
• PhD in Science/Engineering or related field is a plus

Responsibilities

• Physical Implementation activities for high performance GPU Core, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
• Good exposure to PD implementation of PPA critical cores and making right PPA trade-off decisions.
• Strong expertise in timing convergence of high frequency data-path intensive cores and advanced STA concepts
• Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus
• Good understanding of clocking architecture
• Ability to work with design, DFT and PNR teams and resolve constraints validation, verification, STA, PD concerns
• Proficiency in Tcl/Perl scripting
• Experience of working as part of a larger team and delivering milestones
• Strong problem-solving and communication skills

Skills

ASIC design

Verification

Team leadership

Power optimization

Communication

Scripting (Tcl/Perl)

Education

Bachelors/Master’s in Electrical/Electronic Engineering

PhD in Science/Engineering

Tools

Synopsys ICC2

Cadence Innovus

PTSI/Tempus

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Minimum Qualifications

• Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution
• 20+ years of experience in Physical Design/Implementation
• 10 years of experience in leading a team working on high performance cores

Minimum Requirements:

• Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
• Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
• Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
• Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes
• Good understanding of clocking architecture.
• Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
• Well versed with Tcl/Perl Scripting
• Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.
• Strong problem-solving skills and good communication skills.

Applicants:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.