DFT Engineer

NVIDIA Corporation; Hyderabad; Hybrid; INR 1,600,000 - 2,200,000; Full time

Benefits offered by this job

Hybrid work

Job summary

NVIDIA designs for test engineering aims to deliver robust DFT architectures and verification flows for complex semiconductor chips. You will contribute to test access mechanisms, memory BIST, scan compression, and silicon bring-up while collaborating with multi-functional teams.

The role requires 2+ years in DFT, strong HDL/RTL skills, and experience with JTAG standards. Occasional travel and hybrid work model are expected at NVIDIA.

Qualifications

• BSEE or MSEE from reputed institutions or equivalent experience.

Responsibilities

• Design and implement state-of-the-art DFT designs including test access mechanisms, memory BIST and scan compression.

Skills

DFT

RTL verification

HDL design

Scripting

Digital logic

JTAG/IEEE1149.1

Analytical thinking

Communication

Education

BSEE or MSEE

Tools

BIST

Scan ATPG

Job description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you’ll be doing:

• As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression.
• Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
• In addition, you will help develop and deploy DFT methodologies for our next generation products.
• Be apart of innovation to strive improve the quality of DFT methods.
• You will also need to work with multi-functional teams to incorporate DFT features into the chip.
• Occasional travel and also some late hours online meetings involved during critical milestones.

What we need to see:

• BSEE or MSEE from reputed institutions or equivalent experience.
• 2+ Years of experience preferably in Design for testability (DFT)
• You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
• Experience in RTL and Gates verification and simulation.
• You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
• Strong analytical and problem solving skills.
• Expert coding skills in industry standard scripting languages.
• Extraordinary written and oral communication skills with the curiosity to work on rare challenges.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you!

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer.

#LI-Hybrid

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry.

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