DFT Engineer

Renesas Electronics; Bengaluru; Hybrid; INR 4,000,000 - 6,000,000; Full time

Job summary

Renesas Electronics is seeking a senior DFT/PMIC design engineer to join our automotive PMIC team. You will design digital DFT, insert ATPG patterns, and closely coordinate with RTL, test, and silicon validation groups to ensure robust silicon tapeouts.

The candidate will contribute to scan coverage, DFT specification writing, and participate in design reviews while aligning with ASIL requirements and industry tool chains (Synopsys, Cadence, Mentor, Tetramax).

Qualifications

• Master's or Bachelor's with strong digital DFT fundamentals.
• Hands-on experience with Scan insertion and ATPG.
• Experience with Logicbist is highly preferred.
• Gate-level simulations and test pattern delivery to verification teams.
• Proficiency with Verilog, SystemVerilog and RTL coding.

Responsibilities

• Inserting DFT/Scan on digital logic and ATPG.
• Delivering test patterns and validating on silicon.
• Inserting Logicbist with standard tools and improving scan coverage.
• Collaborating with RTL, P&R, test, and silicon validation teams.
• Writing DFT specifications and design collateral.
• Participating in design reviews and checklists.

Skills

digital DFT design

ATPG

Scan insertion

Logicbist

RTL Verilog

SystemVerilog

timing constraints

test patterns

TTD / DFT tools

cross-functional communication

Education

Master's degree in Electrical Engineering

Bachelor's degree in Electrical Engineering

Tools

Synopsys

Cadence

Mentor

Tetramax

Git

SVN

Job description

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Job Description

This is an opportunity to join a top-notch Power Management IC Team with Renesas leading Automotive Business Unit. You will be part of a very skilled group of engineers who are helping build world-class automotive PMIC products that will power tomorrow’s automobiles. You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design – from writing specifications to developing tests for mass production. You will be a key contributor to the digital DFT design team and work closely with the digital design team for meeting TEST requirements for Automobile and work closely with test engineering teams for validating the test patterns and meeting ASIL-B/D requirements. You will have an opportunity to work on new designs, insert Lbist and shape the company’s pathway for success. Your responsibilities, depending on your level of experience and skill level, will be a mix of the following:

• Inserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist.
• Delivering test patterns to TEST engineering team and validating them on silicon.
• Inserting Logicbist with industry standard tools.
• Improving scan coverage and modifying RTL for scan.
• Exposure to automotive test requirements, ASIL, is highly preferred.
• Participate in all aspects of design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog Design, DFT, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC.
• Working closely with Architects, Design, P&R, Test, Silicon validation teams.
• Assisting with top level test-bench creation for scan and running gate level simulations.
• Developing detailed design documents and help writing DFT specification, documents and collateral.
• Holding and participating in key design reviews and completion of various checklists.

Working on-site for 3 days a week is a must.

Qualifications

Following are rough guidelines for the qualifications (if you feel you have much more or somewhat less, let that not stop you from applying):

Required

• Master plus 6+ years or bachelor's plus 8+ years' experience in digital DFT design.
• Must be a team player and yet be an independent thinker with strong digital design and DFT fundamentals
• Hands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist is highly preferred.
• Gate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated.
• Must have basic digital RTL coding experience besides synthesis exposure.
• Must have experience with at least 2 tapeouts with hands on experience with DFT/Scan.
• Ideal candidate will have solid understanding of synthesizable design, timing constraints and how their design implementation looks like on silicon.
• Must have experience with industry standard Synopsys, Cadence, Mentor and other tools used in flows. Tetramax experience is a huge plus.
• Attention to detail, accuracy, and good communication skills
• Must have good written and verbal cross-functional communication skills
• Have an analytical mind - be open to persuasion and have capability to persuade others
• Experience of contributing towards several silicon tapeout cycles from spec to mass production.
• Knowledge of Verilog, Verilog-ams, system verilog.
• Working knowledge of revision control tools such as GIT, SOS or SVN.
• Domain Specific knowledge: A good understanding of one or more than one of the following will be a plus but is not required:
• I2C, SPI, AMBA
• PMIC (Power Management ICs) & Regulators