DFT Engineer

Evollabs Tech; Anupgarh; On-site; INR 3,000,000 - 6,500,000; Full time

Job summary

Evollabs Tech is seeking a Senior DFT Engineer to own design-for-test architecture, implementation, verification, and silicon bring-up for advanced AI SoC/ASIC accelerator designs. You will collaborate across RTL, verification, physical design, product engineering, ATE, and external partners to deliver testable, diagnosable silicon.

Minimum 7+ years of hands-on DFT experience with scan insertion, ATPG, MBIST/LBIST/JTAG, and test-access architectures; strong scripting in Tcl/Python; excellent

Qualifications

• 7+ years of hands-on DFT experience in ASIC or SoC development.
• Strong experience with scan insertion, ATPG, scan compression, fault simulation, and coverage closure.
• Experience with MBIST, LBIST, JTAG, boundary scan, and test access architecture.
• Strong understanding of scan shift/capture timing, at-speed testing, test-mode constraints, and multi-clock-domain DFT.
• Experience debugging DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, and silicon bring-up.
• Experience with complex SoC/IP integration, such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR, or other high-speed interfaces.
• Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, Cadence Modus, or equivalent.
• Strong scripting skills in Tcl, Python, Perl, or shell.
• Excellent written and verbal communication skills, including the ability to work effectively with internal engineering teams, external partners, vendors, and cross-functional stakeholders.

Responsibilities

• Define and implement DFT architectures for complex AI SoC/ASIC blocks and subsystems.
• Own scan insertion, scan compression, ATPG, fault coverage closure, and DFT signoff.
• Implement and support MBIST, LBIST, JTAG, boundary scan, test access, and memory repair features.
• Develop DFT specifications, test plans, coverage targets, constraints, and signoff criteria.
• Work with RTL and verification teams to ensure DFT requirements are built into the design early.
• Collaborate with physical design teams on scan reordering, test-mode timing, congestion, ECOs, and implementation closure.
• Debug DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, physical implementation, and silicon bring-up.
• Support ATE pattern delivery, silicon debug, diagnostics, yield learning, and production test ramp.
• Communicate DFT status, risks, trade-offs, and signoff readiness clearly with internal teams, external partners, vendors, and stakeholders.
• Build scripts and automation to improve DFT implementation, reporting, pattern generation, and debug

Skills

Scan insertion

ATPG

MBIST/LBIST

JTAG/boundary scan

Test access

RTL/verification

Python/Tcl scripting

Multi-clock DFT

Communication

Tools

Siemens Tessent

Synopsys TestMAX/DFT Compiler

Cadence Modus

Job description

About Us

We design and develop customized server hardware solutions optimized for artificial intelligence and machine learning workloads. Our focus is on high-performance, scalable, and energy-efficient infrastructure for next-generation AI compute.

We design and develop customized server hardware solutions optimized for artificial intelligence and machine learning workloads. Our focus is on high-performance, scalable, and energy-efficient infrastructure for next-generation AI compute.

Job Description

Team: SoC Physical Design Team

Type: Full-time – On-site

About Us

We design and develop customized server hardware solutions optimized for artificial intelligence and machine learning workloads. Our focus is on high-performance, scalable, and energy-efficient infrastructure for next-generation AI compute.

Evollabs Tech is hiring a Senior DFT Engineer to own design-for-test architecture, implementation, verification, and silicon bring-up for advanced AI SoC / ASIC accelerator designs.

This role will work across RTL, verification, physical design, product engineering, ATE, and external partners to deliver testable, diagnosable, production-ready silicon.

Responsibilities

• Define and implement DFT architectures for complex AI SoC/ASIC blocks and subsystems.
• Own scan insertion, scan compression, ATPG, fault coverage closure, and DFT signoff.
• Implement and support MBIST, LBIST, JTAG, boundary scan, test access, and memory repair features.
• Develop DFT specifications, test plans, coverage targets, constraints, and signoff criteria.
• Work with RTL and verification teams to ensure DFT requirements are built into the design early.
• Collaborate with physical design teams on scan reordering, test-mode timing, congestion, ECOs, and implementation closure.
• Debug DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, physical implementation, and silicon bring-up.
• Support ATE pattern delivery, silicon debug, diagnostics, yield learning, and production test ramp.
• Communicate DFT status, risks, trade-offs, and signoff readiness clearly with internal teams, external partners, vendors, and stakeholders.
• Build scripts and automation to improve DFT implementation, reporting, pattern generation, and debug

Minimum Qualifications

• 7+ years of hands-on DFT experience in ASIC or SoC development.
• Strong experience with scan insertion, ATPG, scan compression, fault simulation, and coverage closure.
• Experience with MBIST, LBIST, JTAG, boundary scan, and test access architecture.
• Strong understanding of scan shift/capture timing, at-speed testing, test-mode constraints, and multi-clock-domain DFT.
• Experience debugging DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, and silicon bring-up.
• Experience with complex SoC/IP integration, such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR, or other high-speed interfaces.
• Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, Cadence Modus, or equivalent.
• Strong scripting skills in Tcl, Python, Perl, or shell.
• Excellent written and verbal communication skills, including the ability to work effectively with internal engineering teams, external partners, vendors, and cross-functional stakeholders.

Preferred Qualifications (Nice To Have)

• Experience with AI accelerators, GPUs, NPUs, or highly parallel compute SoCs.
• Experience with advanced-node, high-frequency, or high-density designs.
• Experience with chiplets, multi-die systems, UCIe, 2.5D packaging, or package-aware test strategies.
• Experience with HBM/GDDR or other high-bandwidth memory subsystem test requirements.
• Experience with low-power DFT, UPF-aware test implementation, power domains, and power-aware ATPG.
• Experience with silicon bring-up, ATE debug, diagnostics, yield ramp, and production test optimization.
• Prior tapeout experience on advanced-node SoCs.

What Success Really Means

• First silicon is testable, diagnosable, and ready for bring-up without major DFT workarounds.
• DFT coverage targets are met across logic, memory, scan, and relevant fault models.
• Test patterns are delivered on time with acceptable runtime, power, and ATE compatibility.
• Physical design, timing, and manufacturing teams can close signoff without DFT-driven schedule risk.
• Silicon debug and yield learning are accelerated through strong diagnostics and clear test visibility.

Ready to accelerate the future of AI?

Join us in our mission to democratize AI compute — where your DFT expertise helps turn advanced AI silicon into reliable, production-ready infrastructure.

Responsibilities

• Define and implement DFT architectures for complex AI SoC/ASIC blocks and subsystems.
• Own scan insertion, scan compression, ATPG, fault coverage closure, and DFT signoff.
• Implement and support MBIST, LBIST, JTAG, boundary scan, test access, and memory repair features.
• Develop DFT specifications, test plans, coverage targets, constraints, and signoff criteria.
• Work with RTL and verification teams to ensure DFT requirements are built into the design early.
• Collaborate with physical design teams on scan reordering, test-mode timing, congestion, ECOs, and implementation closure.
• Debug DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, physical implementation, and silicon bring-up.
• Support ATE pattern delivery, silicon debug, diagnostics, yield learning, and production test ramp.
• Communicate DFT status, risks, trade-offs, and signoff readiness clearly with internal teams, external partners, vendors, and stakeholders.
• Build scripts and automation to improve DFT implementation, reporting, pattern generation, and debug

Minimum Qualifications

• 7+ years of hands-on DFT experience in ASIC or SoC development.
• Strong experience with scan insertion, ATPG, scan compression, fault simulation, and coverage closure.
• Experience with MBIST, LBIST, JTAG, boundary scan, and test access architecture.
• Strong understanding of scan shift/capture timing, at-speed testing, test-mode constraints, and multi-clock-domain DFT.
• Experience debugging DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, and silicon bring-up.
• Experience with complex SoC/IP integration, such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR, or other high-speed interfaces.
• Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, Cadence Modus, or equivalent.
• Strong scripting skills in Tcl, Python, Perl, or shell.
• Excellent written and verbal communication skills, including the ability to work effectively with internal engineering teams, external partners, vendors, and cross-functional stakeholders.

Preferred Qualifications (Nice To Have)

• Experience with AI accelerators, GPUs, NPUs, or highly parallel compute SoCs.
• Experience with advanced-node, high-frequency, or high-density designs.
• Experience with chiplets, multi-die systems, UCIe, 2.5D packaging, or package-aware test strategies.
• Experience with HBM/GDDR or other high-bandwidth memory subsystem test requirements.
• Experience with low-power DFT, UPF-aware test implementation, power domains, and power-aware ATPG.
• Experience with silicon bring-up, ATE debug, diagnostics, yield ramp, and production test optimization.
• Prior tapeout experience on advanced-node SoCs.

What Success Really Means

• First silicon is testable, diagnosable, and ready for bring-up without major DFT workarounds.
• DFT coverage targets are met across logic, memory, scan, and relevant fault models.
• Test patterns are delivered on time with acceptable runtime, power, and ATE compatibility.
• Physical design, timing, and manufacturing teams can close signoff without DFT-driven schedule risk.
• Silicon debug and yield learning are accelerated through strong diagnostics and clear test visibility.

Ready to accelerate the future of AI?

Join us in our mission to democratize AI compute — where your DFT expertise helps turn advanced AI silicon into reliable, production-ready infrastructure.