Design Engineer II

Cadence Design Systems, Inc.; Pune City; On-site; INR 8,00,000 - 12,00,000; Full time

Job summary

A leading technology company in Pune is seeking an experienced RTL Design Engineer. The role requires 3 to 6 years of experience in RTL Design and integration, with proficiency in Verilog/System-Verilog. The selected candidate will work closely with architects and the verification team to ensure high design quality. Candidates should exhibit excellent communication skills and a self-motivated attitude.

Qualifications

• 3 to 6 years of actual work experience in RTL Design.
• Thorough understanding of end-to-end Digital design flow.
• Responsibilities in Verilog / System-Verilog RTL logic design.

Responsibilities

• Responsible for RTL Design & Integration.
• Perform Lint and CDC checks to achieve required design quality.
• Work closely with Architects and Verification team.

Skills

RTL Design

Verilog

System-Verilog

Digital design flow

Lint checks

Communication skills

Education

BTech/ MTech in Engineering

Job description

Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

• Selected Candidate is responsible for RTL Design & Integration. Needs to work closely with Architects and Verification team.
• Responsible to achieve required design quality by performing Lint and CDC checks and adhering to release checklists.
• Exhibit excellent communication skills and be self-motivated and well organized.
• We’re doing work that matters. Help us solve what others can’t.

Qualifications

• BTech/ MTech in Engineering with 3 to 6 years of actual work experience in RTL Design.
• The ideal candidate should have thorough understanding of end-to-end Digital design flow.
• Verilog / System-Verilog RTL logic design, debug, and functional verification support.
• Understanding of proper handling of multiple asynchronous clock domains and their crossings.
• Understanding of Lint checks and proper resolution of errors.
• Working experience on APB and AXI protocols.
• Working experience on micro-controller based designs and its associated logic is a Strong plus.
• Experience in Digital microarchitecture definition and documentation is a plus.
• Experience in synthesis timing constraints, static timing analysis and constraint development is a plus.
• Experience with FPGA and/or emulation platform is a plus.

Equal Employment Opportunity

Cadence is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, disability, or any other protected class.