CPU Design Verification Assoc Engineer

Qualcomm; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Qualcomm India Private Limited is seeking DV engineers to verify high-performance, low-power CPUs in Bangalore. You will drive power management verification across boot, clock gating, UPF usage, and DVFS with design/verification teams.

Responsibilities include creating test plans, writing checkers and assertions, and validating system use cases on emulators/FPGA, collaborating with CPU, SoC, and software teams, and debugging across simulators and silicon.

Qualifications

• Bachelor's or higher degree in CS/EE or related field with hardware verification experience
• Masters/PhD beneficial for advanced verification
• BE/BTech CS/EE with extensive experience
• Experience with power management verification and embedded firmware
• Proficiency in C/C++, Verilog/SystemVerilog and scripting languages

Responsibilities

• Verify power management features (Boot, Reset, clock gating, power gating) and DVFS control.
• Develop test plans with design/verification teams for CPU hardware.
• Write checkers, assertions, and stimuli to validate power intent.
• Verify UPF-based power intent and related architecture.
• Collaborate with system architects, software, and SoC teams for use-case validation.
• Coordinate with emulation team to enable verification on emulators/FPGA.
• Debug and triage failures across simulation, emulation, and silicon.

Skills

Power management verification

C/C++

Verilog/SystemVerilog

Embedded firmware (assembly/C)

Test planning

UPF/DVFS

Debug and triage

Education

Bachelor's degree in CS/EE

Master's degree in CS/EE

PhD in CS/EE

BE/BTech CS/EE 12+ years

Tools

Emulation platforms

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.

Roles and Responsibilities

• Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.
• Work closely with design/verification teams within CPU to develop comprehensive test plan.
• Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.
• Verify power intent through use of methodologies like UPF.
• Work closely with system architects, software teams and Soc team to validate system use cases.
• Work closely with emulation team to enable verification on emulators and FPGA platforms.
• Debug and triage failures in simulation, emulation and/or Silicon.

Minimum Qualifications:

• • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• BE/BTech degree in CS/EE with 12+ years’ experience.
• Experience in power management verification.
• Implementation of assembly and C language embedded firmware.
• Experience in C/C++, scripting languages, Verilog/system Verilog.
• Strong understanding of power management features in CPUs and CPU based Socs.
• Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Preferred Requirements:

• Good Understanding of CPU architectures and CPU micro-architectures.
• In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture
• Experience with advanced verification techniques such as formal and assertions is a plus
• Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

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