Compiler Engineer (GPU Backend)

Oxmiq Labs; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Equity participation

Medical coverage

Job summary

Oxmiq Labs in Hyderabad, India is seeking an experienced Compiler Engineer (GPU Backend) to design and implement compiler infrastructure for GPU-accelerated workloads. You will contribute to lowering pipelines, optimization passes, and code generation backends, working with MLIR/LLVM style frameworks, and collaborating with hardware teams.

The role requires 5+ years in compiler engineering, strong C++, and experience with GPU/NPU backends, Triton/CUDA, and performance profiling.

Qualifications

• 5+ years of compiler engineering experience with GPU/NPU/AI accelerators.
• Strong proficiency in C++.
• Experience with MLIR/LLVM/TVM/IREE or similar frameworks.
• Knowledge of IR transformations, code generation, scheduling, and memory hierarchies.

Responsibilities

• Design and implement compiler infrastructure for GPU workloads.
• Develop optimization passes and code generation backends.
• Optimize segmentation, scheduling, and tiling for Oxmiq hardware.
• Collaborate with architecture and kernel teams on performance requirements.
• Support Triton-based models and integration with LLM serving stacks.

Skills

C++

Compiler frameworks

GPU/AI acceleration

IR transformations

CUDA/Triton

Performance profiling

Python scripting

Claude Code

Education

B.E./B.Tech/M.E./M.Tech/MS/Ph.D. in CS/CE/EE

Tools

LLVM

MLIR

TVM

IREE

Job description

Compiler Engineer (GPU Backend)

Oxmiq Labs | Hyderabad, India (On-site)

Experience: 5+ Years

Key Responsibilities

• Design and implement compiler infrastructure for GPU-accelerated workloads, including lowering pipelines, optimization passes, and code generation backends.
• Develop and optimize compilation passes targeting Oxmiq hardware IP and GPU architectures.
• Design and implement segmentation and scheduling strategies for the Oxmiq hardware backend to maximize hardware utilization, throughput, and execution efficiency.
• Develop compiler optimizations for operator fusion, tiling, memory planning, and workload partitioning across GPU hardware.
• Collaborate with architecture and hardware teams to translate performance requirements into efficient compiler transformations and code generation strategies.
• Work with kernel engineers to support Triton-based programming models, custom operator lowering, and integration with modern LLM serving frameworks such as vLLM and SGLang.
• Optimize compiler output for throughput, latency, memory efficiency, and scalability across AI workloads.
• Participate in architecture discussions, design reviews, and code reviews.
• Support compiler performance profiling, benchmarking, debugging, and root cause analysis.

Required Qualifications

• 5+ years of experience in compiler engineering, with a focus on GPU, NPU, or AI accelerator software stacks.
• Strong proficiency in C++.
• Hands-on experience with at least one modern compiler framework such as MLIR, LLVM, TVM, or IREE.
• Experience designing or implementing compiler optimizations, scheduling algorithms, segmentation/partitioning strategies, or lowering pipelines for GPU/NPU hardware.
• Solid understanding of compiler concepts including IR transformations, code generation, instruction scheduling, register allocation, vectorization, and memory hierarchy optimization.
• Familiarity with GPU programming models such as CUDA or Triton.
• Understanding of GPU architecture fundamentals including thread execution models, memory systems, occupancy, synchronization, and performance bottlenecks.
• Experience optimizing compiler-generated code for performance on modern GPU or AI accelerator hardware.
• Strong debugging, profiling, and performance analysis skills.
• Hands-on experience with Claude Code or equivalent AI-assisted software development workflows.

Preferred Qualifications

• Experience developing compiler backends for custom AI accelerators, NPUs, or GPU IP.
• Experience with Triton compiler internals or other high-level GPU kernel frameworks.
• Familiarity with kernel fusion, operator tiling, graph partitioning, auto-tuning, and workload scheduling.
• Exposure to quantization, mixed precision, sparsity-aware compilation, or memory optimization techniques.
• Experience integrating compiler technology with LLM serving frameworks such as vLLM or SGLang.
• Experience with performance modeling, roofline analysis, or hardware-aware optimization.
• Contributions to open-source compiler projects such as LLVM, MLIR, TVM, Triton, or IREE.
• Python scripting experience for compiler tooling, testing, automation, or benchmarking.

Education

• B.E./B.Tech/M.E./M.Tech/MS/Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field.

Working Environment

The successful candidate will work within a compact, senior team comprising compiler engineers, hardware architects, and kernel authors. A senior compiler engineer will serve as the primary technical mentor, providing direction, code review, and guidance across MLIR, LLVM backend development, and GPU code generation on production silicon.

Compensation & Benefits

OXMIQ offers a competitive compensation package, including base salary, equity participation, comprehensive medical coverage, and the opportunity to contribute to foundational silicon and software technology.

OXMIQ is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected characteristic.