CAD Engineer (Staff / Senior Staff)

TYLsemi; Bengaluru; Hybrid; INR 4,000,000 - 8,000,000; Full time

Job summary

TYLsemi is seeking an experienced Staff/Senior Staff CAD Engineer to lead VLSI CAD methodologies and automation across RTL-to-GDS flows. You will collaborate with Physical Design, Frontend, DFT, STA, and EDA vendors to drive scalable CAD infrastructure for tape-outs of complex SOCs.

The role emphasizes design productivity, QoR improvements, and tool-flow debugging with a global, remote-friendly team. Prior experience with Cadence, Synopsys, and Siemens EDA is essential.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Computer Engineering, VLSI, or related field.
• 8 to 15+ years of CAD engineering, physical design methodology, or EDA flow development.
• Strong expertise in ASIC/SOC implementation flows including synthesis, P&R, STA, physical verification, and low-power methodologies.
• Hands-on experience with Cadence, Synopsys, and Siemens EDA tool suites.
• Strong programming and scripting in Tcl, Python, Perl, and Shell scripting.
• Experience with distributed computing environments, regression frameworks, and infrastructure management.
• Strong debugging, analytical, communication, and stakeholder management skills.

Responsibilities

• Architect, develop, and maintain scalable CAD flows for synthesis, physical design, STA, low-power verification, and signoff.
• Drive automation and methodology improvements to enhance design efficiency, runtime, and QoR.
• Collaborate with design, verification, DFT, and implementation teams to understand flow requirements and deployment challenges.
• Debug complex flow, tool, and infrastructure-related issues across project execution.
• Integrate and qualify new EDA tool releases and advanced node methodologies.
• Develop automation scripts, regression environments, dashboards, and flow monitoring infrastructure.
• Work with foundries and EDA vendors on technology enablement and issue resolution.
• Mentor engineers and establish CAD best practices across teams.

Skills

Tcl

Python

Perl

Shell scripting

Debugging

Stakeholder management

Education

Bachelor’s or Master’s degree in Electronics/CE/VLSI

Tools

Cadence

Synopsys

Siemens EDA

Job description

Role Overview

We are seeking an experienced Staff / Senior Staff CAD Engineer to lead the development, deployment, and support of advanced VLSI CAD methodologies and automation solutions. The role focuses on improving design productivity, quality, and scalability across RTL-to-GDS implementation flows. The ideal candidate will work closely with Physical Design, Frontend, DFT, STA, and EDA vendors to drive robust CAD infrastructure and enable successful tape-outs for complex SOCs.

What You’ll Do

• Architect, develop, and maintain scalable CAD flows for synthesis, physical design, STA, low-power verification, and signoff.
• Drive automation and methodology improvements to enhance design efficiency, runtime, and QoR.
• Collaborate with design, verification, DFT, and implementation teams to understand flow requirements and deployment challenges.
• Debug complex flow, tool, and infrastructure-related issues across project execution.
• Integrate and qualify new EDA tool releases and advanced node methodologies.
• Develop automation scripts, regression environments, dashboards, and flow monitoring infrastructure.
• Work with foundries and EDA vendors on technology enablement and issue resolution.
• Mentor engineers and establish CAD best practices across teams.

What We’re Looking For

• Bachelor’s or Master’s degree in Electronics, Computer Engineering, VLSI, or related field.
• 8 to 15+ years of experience in CAD engineering, physical design methodology, or EDA flow development.
• Strong expertise in ASIC/SOC implementation flows including synthesis, P&R, STA, physical verification, and low-power methodologies.
• Hands‑on experience with industry-standard EDA tools such as Cadence, Synopsys, and Siemens EDA tool suites.
• Strong programming and scripting skills in Tcl, Python, Perl, and Shell scripting.
• Experience with distributed computing environments, regression frameworks, and infrastructure management.
• Strong debugging, analytical, communication, and stakeholder management skills.

Good to Have

• Experience with cloud‑enabled EDA infrastructure and workload management systems.
• Exposure to AI/ML‑driven CAD optimization methodologies.
• Knowledge of advanced technology nodes (5nm/3nm) and multi‑die design flows.

Success in This Role Looks Like

• Delivery of stable, scalable, and high‑quality CAD flows adopted across multiple projects.
• Significant improvements in design productivity, QoR, and runtime efficiency.
• Fast resolution of tool and flow issues minimizing project execution risk.
• Strong technical leadership, mentoring, and positive influence on engineering methodology.

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That’s what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

Why Now

The Market Window

• Moore’s Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they’re all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We’re entering the market at exactly the moment when every major AI/HPC player needs what we’re building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world‑class design center in Bangalore

Move Fast, Ship Real Products

We’re not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We’re building to win.

What We Value

• Ownership mindset. You’re not here to execute someone else’s roadmap. You’re here to define it.
• Bias for action. We move fast. Analysis paralysis doesn’t fly here.
• Deep technical expertise. This is hard engineering. We need people who’ve shipped real silicon and debugged real hardware.
• Low ego, high standards. We don’t care about titles or politics. We care about results.

The Ask

If you’re reading this, you’re probably comfortable. You have a good job at a stable company with all the benefits.

We’re asking you to walk away from that and bet on us.

Here’s Why You Should

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we’re building.
• The team has done this before. We’ve built and exited semiconductor companies at scale. This isn’t our first rodeo.
• The traction is de‑risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You’re not optimizing someone’s ad click‑through rate. You’re building the silicon infrastructure that powers AI.

READY TO JOIN?