Staff - SoC RTL Design Engineer (UCIE)

TYLsemi; Bengaluru; Hybrid; INR 2,400,000 - 4,000,000; Full time

Job summary

TYLsemi is seeking a highly skilled RTL Designer to develop high-performance, power-efficient digital designs for next-generation SoCs and chiplets. You will own reset sequencing, clocking, power management, and firmware interfaces across multi-power-domain architectures.

The role requires 8+ years in digital IC design with at least 3 years leading chip infrastructure and strong SystemVerilog skills. Expect collaboration with firmware and physical design teams to ensure first-time silicon

Qualifications

• 8+ years of digital IC design experience
• 3+ years owning chip infrastructure (clocking, power mgmt, reset/DFT) at block-lead level
• Strong SystemVerilog for infrastructure RTL
• Familiarity with embedded MCU integration and firmware bring-up

Responsibilities

• Specify and own reset sequencing architecture and secure boot/fuse MCU design.
• Coordinate clock distribution and clock-domain crossing at subsystem interfaces.
• Define hardware/software interfaces: interrupt controller, timer, UART/JTAG, DMA, mailbox channels.
• Own clock-gating strategy and sign-off for dynamic power reduction.
• Define chip-level power-domain plan and power-state mappings for PCIe/UCIe links.
• Manage on-chip power management logic and firmware runtime control.
• Drive UPF/CPF power intent authoring with PD floorplan coordination.
• Oversee embedded management processor subsystem integration and boot sequence.
• Define management register map for firmware configuration and telemetry.
• Oversee thermal monitoring integration and throttling hooks.

Skills

Digital IC design

SystemVerilog

Clocking

Power management

Reset architecture

DFT

Embedded MCU integration

Education

BS/MS in Electrical or Computer Engineering

Tools

SystemVerilog tools

Job description

Role Overview

We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targeting AI, HPC, and Networking applications. This role requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on quality, performance, and first-time silicon success.

What You’ll Do

• Specify and own the reset sequencing architecture. Own the secure boot and fuse micro architecture and design.
• Coordinate with the subsystem leads on reference clock distribution, clock-domain crossing points at subsystem interfaces.
• Collaborate with the firmware team to define the hardware/software interface: interrupt controller, timer, UART/JTAG debug port, and any DMA or mailbox channels
• Own the clock-gating implementation strategy: coarse-grain vs. fine-grain gating, ICG cell selection, and sign-off methodology for dynamic power reduction.
• Define the chip-level power-domain plan: which blocks share supplies, where level-shifters and isolation cells are required, and how power states map to the PCIe and UCIe link power management protocols.
• Own the on-chip power management logic: power-state machine, supply sequencing, voltage regulator integration, and the firmware interface for runtime power control.
• Drive power intent (UPF/CPF) authoring and sign-off, coordinating with physical design team on power-domain floorplan, always-on routing, and isolation verification.
• Own the embedded management processor subsystem: processor integration, on-chip SRAM and ROM sizing, boot sequence, fuse and OTP interface, and the firmware execution environment.
• Define the management register map: the address space through which firmware configures operating modes, reads telemetry, controls power states, and manages DFT operations.
• Specify thermal monitoring integration: on-die temperature sensor placement, readout path to the management processor, and thermal throttling hooks.

What We’re Looking For

• 8+ years of digital IC design, with at least 3 years owning chip infrastructure — clocking, power management, reset or DFT — at block-lead or subsystem-owner level.
• Familiarity with embedded microcontroller integration: memory maps, boot ROM, interrupt controllers, and firmware bring-up at the hardware level.
• Experience with reset-domain architecture and reset synchronizer design in multi-power-domain chips.
• Strong SystemVerilog skills for infrastructure RTL: clock-gating cells, power FSMs, scan-enable muxing, and BIST controllers.
• BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Good to Have

• Background integrating a RISC‑V or ARM Cortex‑M class processor as a management/configuration engine in a non‑CPU chiplet.
• Exposure to hardware security: secure boot, anti‑tamper fuse programming, or related infrastructure.

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world‑class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

Here’s Why You Should

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet.

Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?