ASIC Technical Program Manager (TPM)

Intellics Global Services; Ernakulam, Hyderabad; Hybrid; INR 4,000,000 - 6,000,000; Full time

Job summary

Intellics Global Services in India seeks an experienced leader to own end-to-end delivery of turnkey ASIC/SoC programs, from specification to tape-out and post-silicon bring-up across RTL, DV, DFT, PD and validation teams. You will lead cross-functional teams, drive milestones, run gated reviews, and manage scope, risks and dependencies with customers and OSAT partners.

The ideal candidate has 15+ years in semiconductors, strong command of the full ASIC flow, and hands-on experience with

Qualifications

• 15+ years in semiconductors; experience leading ASIC/SoC programs through multiple tape-outs.
• Strong command of the full ASIC flow: architecture, RTL, DV, DFT, PD, signoff, post-silicon.
• Proven ability to estimate effort, manage budgets and risks on fixed-price or turnkey engagements.

Responsibilities

• Own the program plan, milestones and critical path from architecture freeze through tape-out and silicon bring-up.
• Drive cross-functional execution across RTL, DV, DFT, PD, SW/FW and validation teams.
• Run gated reviews (spec, RTL freeze, DFT, signoff, tape-out) and enforce exit criteria.
• Manage scope, risks, dependencies and change control with customers, foundry and OSAT partners.
• Forecast effort and capacity; align staffing, EDA tools and IP with the plan.
• Report schedule, quality and risk status to customer and leadership; escalate early.

Skills

Semiconductor experience

Program leadership

Cross-functional leadership

Customer-facing communication

Tools

Jira

MS Project

Job description

Role & responsibilities

Experience

15+ years

Location

HYDERABAD, KOCHI, CHENNAI, BANGALORE ,PUNE

Domain

ASIC / SoC Turnkey Silicon

Employment

Full-time

The Role

Own end-to-end delivery of turnkey ASIC/SoC programs, from specification to tape-out and post-silicon bring-up, across RTL, DV, DFT, PD and validation teams.

What You Will Do

• Own the program plan, milestones and critical path from architecture freeze through tape-out and silicon bring-up.
• Drive cross-functional execution across RTL, DV, DFT, PD, SW/FW and validation teams.
• Run gated reviews (spec, RTL freeze, DFT, signoff, tape-out) and enforce exit criteria.
• Manage scope, risks, dependencies and change control with customers, foundry and OSAT partners.
• Forecast effort and capacity; align staffing, EDA tools and IP with the plan.
• Report schedule, quality and risk status to customer and leadership; escalated early.

What You Bring

• 15+ years in semiconductors, with 8+ years leading ASIC/SoC programs through at least two tape-outs.
• Strong command of the full ASIC flow: architecture, RTL, DV, DFT, PD, signoff, post-silicon.
• Hands-on with tape-out gating, signoff criteria and the foundry/OSAT interface (masks, packaging, test).
• Proven effort estimation, budget tracking and risk management on fixed-price or T&M turnkey engagements.
• Confident, customer-facing communicator who can hold senior technical and business conversations.
• Proficiency with Jira, MS Project or equivalent planning tools.

Good to Have

• PMP / PgMP certification
• Experience with advanced nodes or multi-die / chiplet programs
• Exposure to post-silicon validation and production ramp

Preferred candidate profile

Perks and benefits