ASIC RTL Engineer

Talent Worx; Ernakulam; On-site; INR 8,00,000 - 15,00,000; Full time

Job summary

A technology solutions company is seeking an experienced ASIC RTL Engineer in Kerala, India. The candidate should have a strong background in SoC design and expertise in Verilog/System Verilog. Responsibilities include setting up RTL quality checks and supporting various teams. Proficiency in scripting languages and experience with tools like Spyglass Lint is essential.

Qualifications

• Experience with ASIC RTL Engineering and SoC subsystem/IP design.
• Expertise in Verilog/System Verilog for IP design and integration.
• Knowledge of timing concepts and RTL quality checks.

Responsibilities

• Set up and use tools like Spyglass Lint/CDC, Synopsys DC.
• Understand scripting languages such as Make flow, Perl, shell, python.
• Support physical design, verification, and software teams.

Skills

RTL

Coding

Design

IP Design

SOC Development

Lint

CDC

Micro Architecture

PCIe

DDR

Ethernet

I2C

UART

SPI

Spyglass Lint/CDC

Synopsys DC

Verdi/Xcellium

Make flow

Perl

Shell

Python

Tools

Spyglass Lint/CDC

Synopsys DC

Verdi/Xcellium

Job description

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC, Micro Architecture - Mandatory

Preferred skills include:

• PCIe
• DDR
• Ethernet

And one of the following:

• I2C
• UART
• SPI

Additionally, experience with one of the following tools is preferred:

• Spyglass Lint/CDC
• Synopsys DC
• Verdi/Xcellium

And proficiency in one of the following scripting languages:

• Make flow
• Perl
• Shell
• Python

Responsibilities include:

• ASIC RTL Engineer with expertise in SoC subsystem/IP design
• Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
• In-depth knowledge of RTL quality checks (Lint, CDC)
• Knowledge of synthesis and low power is a plus
• Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
• Good understanding of timing concepts
• Knowledge of one or more of the interface protocols

The ideal candidate will be able to:

• Set up and use tools like Spyglass Lint/CDC, Synopsys DC, Verdi/Xcellium
• Understand scripting languages like Make flow, Perl, shell, python
• Understand processor architecture and/or ARM debug architecture
• Help and debug issues for multiple subsystems
• Create/review design documents for multiple subsystems
• Support physical design, verification, DFT and SW teams on design queries and reviews