ASIC Physical Design, Manager

Synopsys, Inc.; Bengaluru; On-site; INR 4,500,000 - 7,000,000; Full time

Benefits offered by this job

Health benefits

Financial benefits

Job summary

Synopsys, Inc. seeks an experienced Physical Design Manager to lead a team responsible for the PD flow from RTL handoff to GDSII delivery.

You will drive end‑to‑end testchip projects, oversee timing closure, power optimization, and physical verification, and collaborate with front‑end, silicon validation, and software teams to ensure successful tape‑outs. You will mentor engineers, set up automation flows, and tackle complex timing paths with judgment and speed, while growing leaders within the

Qualifications

• 8 to 14 years of hands‑on experience in ASIC physical design
• Proven track record of multiple successful tape outs across process nodes
• Deep expertise in physical design implementation, timing closure, and power optimization
• Strong understanding of RTL to GDSII flow, handoff points, and verification stages
• Experience setting up design automation flows and scripting for PD tasks
• Front‑end design or RTL experience is a plus and helps bridge intent with hardware
• Demonstrated ability to manage people, projects, and cross‑functional collaboration

Responsibilities

• Lead a team of physical design engineers and own the complete PD flow from RTL handoff to GDSII delivery
• Drive end‑to‑end execution of multiple testchip projects including timing closure, power optimization, and physical verification
• Set up and continuously improve PD design automation flows and scripting for repeatability
• Collaborate with front‑end design, silicon validation, and software teams to align on design intent
• Manage project schedules, resource allocation, and risk to meet tape‑out dates while maintaining quality
• Mentor engineers on timing analysis, floorplanning, place and route strategies, and verification best practices
• Build depth and judgment across the team and foster a culture of ownership and learning

Skills

People leadership

Team management

Mentoring

Cross-functional collaboration

Problem solving

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Fusion Compiler

ICC2

PrimeTime

Calibre

Tempus

Job description

Alternate Job Titles

• Physical Design Manager
• ASIC PD Lead
• Physical Implementation Manager
• Backend Design Manager
• Physical Design Engineering Manager

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of ASIC physical design, and you know that tape out success is not about heroics at the end, it is about the flow you set up, the checks you automate, and the decisions you make when the schedule says one thing and the timing report says another. You have managed teams through multiple silicon cycles and learned that the best managers do not just delegate tasks, they clear blockers, teach judgment, and know when to dive into a floorplan yourself because it is faster than explaining it three times.

You think in terms of flows, not just milestones. Setting up a robust RTL-to-GDSII methodology for a testchip team means anticipating where the pain will come from, whether that is a tricky timing path, a foundry DRC that changed mid-project, or a handoff that breaks because someone assumed too much. You are comfortable sitting with front-end designers to understand intent and then translating that into a physical implementation strategy that actually closes.

Managing people energizes you. You hire well, you grow engineers into leads, and you know the difference between mentoring someone through a tough closure and doing it for them. At Synopsys, you will lead a team building testchips that prove out next-generation embedded memory IP, and what you deliver will directly enable customer products.

What You’ll Be Doing

• Lead a team of physical design engineers responsible for building and maintaining the complete PD flow and methodology for the Testchip team, from RTL handoff through GDSII delivery
• Drive end-to-end execution of multiple testchip projects, managing timing closure, power optimization, and physical verification using tools like ICC2, Fusion Compiler, PrimeTime, and Calibre
• Set up and continuously improve design automation flows across physical design stages, including scripting for repeatability, quality checks, and faster closure cycles
• Collaborate with front-end design, silicon validation, and software teams to align on design intent, verify handoffs, and troubleshoot issues that span multiple domains
• Manage project schedules, resource allocation, and risk mitigation to hit tape out dates while maintaining quality and design robustness
• Serve as the technical point of contact for foundry interactions, translating foundry requirements into actionable design constraints and managing DRC/LVS closure
• Mentor engineers on timing analysis, floorplanning, place and route strategies, and verification best practices, building depth and judgment across the team

The Impact You Will Have

• Deliver high-quality, high-performance testchips that validate Synopsys embedded memory IP and enable faster customer adoption of next-generation products
• Accelerate time-to-market for Synopsys customers by ensuring robust, repeatable tape outs that meet performance, power, and area targets
• Strengthen Synopsys technical reputation through successful project delivery, post-silicon support, and proactive customer engagement
• Drive measurable improvements in physical design methodology, reducing closure time, improving PPA, and increasing automation across the testchip flow
• Grow engineering talent within the organization by mentoring engineers into technical leads and building a culture of ownership and continuous learning
• Influence future product direction by feeding silicon learnings back into IP development and strategic planning discussions
• Build stronger foundry partnerships through technical collaboration, early engagement on process nodes, and clear communication during bring-up and debug

What You’ll Need

• 8 to 14 years of hands‑on experience in ASIC physical design, with at least 2 years leading teams or managing projects
• Proven track record of multiple successful tape outs, ideally across different process nodes or design complexities
• Deep expertise in physical design implementation, timing closure, power optimization, and physical verification using industry‑standard EDA tools like Fusion Compiler, ICC2, PrimeTime, Tempus, Calibre, or equivalent
• Strong understanding of the complete chip design flow from RTL to GDSII, including handoff points, verification stages, and common failure modes
• Experience setting up design automation flows, scripting for physical design tasks, and improving methodology for timing closure and verification
• Experience in front‑end design or RTL methodologies is a significant plus and will help you bridge design intent with physical implementation
• Demonstrated ability to manage people, projects, and cross‑functional collaboration in a technical environment with competing priorities

Who You Are

• You lead by teaching, not just assigning. When an engineer is stuck on a timing path, you sit with them, walk through the analysis, and make sure they understand why the fix works, not just what to change
• You communicate complex tradeoffs clearly. Whether it is explaining a floorplan decision to a front‑end designer or a schedule risk to a program manager, you get to the point without losing the technical nuance
• You are detail‑oriented but not paralyzed by it. You know when to dig into a Calibre DRC violation yourself and when to trust your team to close it
• You make decisions with incomplete information. Testchip schedules do not wait for perfect data, and you are comfortable making a call, documenting the rationale, and adjusting if new information changes the picture
• You build teams that want to work with you. People stay on your projects because they learn, because you clear obstacles, and because you give credit where it belongs
• You stay current. You know what is changing in physical design tools, foundry processes, and industry best practices, and you bring that knowledge back to improve how your team works

The Team You’ll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.