ASIC Physical Design Engineer

InCommon; India; Remote; INR 900,000 - 1,800,000; Full time

Job summary

InCommon, on behalf of a California based company, seeks a hands-on VLSI Physical Design Engineer for India-based remote work. 5+ years of experience and a B.S. in Electrical Engineering are required.

Responsibilities include end-to-end physical design flow, floorplanning, placement, CTS, routing, timing closure, and tapeout across multiple PVT corners, using Cadence Innovus and timing tools. Strong scripting and low-power experience are preferred.

Qualifications

• Advanced-node tapeout experience across 7nm, 12nm, 22nm nodes.
• Proficient in Cadence Innovus for P&R, optimization, CTS, routing and ECO.
• Timing closure across modes and PVT with MMMC methodology.
• UPF low-power design flow from RTL to P&R with power intent.

Responsibilities

• Own complete SoC physical design flow from netlist to tapeout.
• Perform floorplanning, macro placement, IO/pin planning, power-grid design.
• Drive place and route, physical optimization, CTS, routing, ECO.
• Close timing across multiple modes and PVT corners (MMMC).
• Run LVS/DRC/antenna checks; fix foundry rule violations in Innovus.
• Run RC extraction and IR-drop/electromigration analysis.
• Do RTL- and gate-level power analysis and collaborate with RTL team.
• Participate in tapeout readiness reviews and signoff.

Skills

Tapeout experience

Timing closure

Scripting (Tcl, Python)

RTL expertise

Power/low-power design

AI tooling for design

Education

B.S. in Electrical Engineering

Tools

Cadence Innovus

PrimeTime

Tempus

Job description

PIMIC is building the compiler that brings Processing-in-Memory AI to life.

InCommon is hiring on behalf of a California based company that is building ultra-low-power neural processing technology for edge AI — chips that run advanced AI workloads within tight power and memory budgets. The Processing-in-Memory (PIM) architecture computes directly inside memory, breaking the traditional bottleneck of shuttling data back and forth.

Role : VLSI Physical Design Engineer

India-based Remote

5+ years, hands-on | Full -time

B.S. in Electrical Engineering

Requirements:

• Advanced-node tapeout experience — ideally 7nm, 12nm, 22nm
• Extensive hands‑on Cadence Innovus (P&R, physical optimization, CTS, routing, ECO)
• Timing closure across multiple modes and PVT corners using PrimeTime or Tempus with MMMC methodology
• UPF low‑power design flow from synthesis through P&R — able to develop and debug UPF from RTL power-domain specs and power intent
• Strong Tcl scripting, plus at least one of Python / Perl / shell
• B.S. in Electrical Engineering

Strongly preferred

• Multiple successful SoC/ASIC tapeouts at 12nm, including full chip‑level ownership
• Hierarchical and flat physical design methodologies
• Complex multi‑voltage, multi‑power‑domain SoCs
• High‑speed interface experience (PCIe or other complex IP)
• Mixed‑signal integration — signal/noise isolation, analog‑digital power isolation, impedance matching, differential routing
• Familiarity with DFT, scan, CDC/reset, package constraints, bump planning, wirebond, WLCSP, or flip‑chip
• RTL expertise
• Experience using AI/agentic tooling to cut design-cycle time and reduce errors

What you’ll do

• Own the complete SoC physical design flow, from netlist and UPF handoff through floorplanning, placement, CTS, routing, ECO, timing closure, physical verification, signoff, and tapeout.
• Perform chip- and block-level floorplanning, macro placement, I/O and pin planning, power-domain planning, power-grid design, congestion analysis, and routing‑resource planning.
• Drive place and route, physical optimization, CTS, routing, and ECO implementation in Cadence Innovus.
• Close timing across multiple modes and PVT corners using PrimeTime or Tempus (MMMC).
• Set up, run, debug, and close Calibre LVS, DRC, antenna, wirebond, and WLCSP checks; interpret foundry rules and implement manual or automated fixes in Innovus.
• Run RC extraction (Quantus) and IR‑drop / electromigration analysis (Voltus).
• Perform RTL‑and gate‑level power analysis (Joules).
• Collaborate with RTL and verification engineers, using Xcelium or VCS waveforms to debug logic, timing, and integration issues.
• Participate in tapeout readiness reviews and ensure timing, physical verification, power integrity, low‑power, and foundry signoff requirements are complete.
• Use AI responsibly to find solutions that save cycle time and reduce human error.

Who thrives here

Highly hands‑on, detail‑oriented, and technically rigorous. Able to independently troubleshoot difficult design and signoff problems with minimal supervision. Strong ownership mindset — drives assigned blocks or chip‑level responsibilities through to closure. A clear communicator who works well across front‑end, verification, DFT, package, CAD, and foundry teams, and who’s comfortable prioritizing multiple closure issues under schedule pressure.

Why this role

Small, fast‑moving team building genuinely novel silicon. Real ownership from day one.