ASIC Engineering Technical Leader | Physical Design | Floor Planning | GSP & PD | Exp - 11+ years

123 Cisco Systems (India) Private Limited; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Cisco Systems’ Bangalore team seeks an experienced ASIC Physical Design Engineer to drive RTL2GDS implementation across floor planning, place & route, timing closure and sign-off for advanced nodes.

You will collaborate with RTL, DFT, tool owners and EDA vendors to improve methodologies and automate workflows. Strong scripting in TCL/Shell/Perl/Python is essential for automation and debugging.

Qualifications

• 13+ years of ASIC physical design experience.
• Experience with full RTL2GDS implementation flow.
• Experience with large-scale designs (<100M gates) and sub-16/14/7/5/3nm nodes.
• Strong scripting skills in TCL/Shell/Perl/Python.
• Familiarity with Design for Yield and Manufacturability, CTS strategies, and ECO flows.

Responsibilities

• Drive the physical design flow from RTL to GDSII, including floor planning, place & route, timing closure and sign-off.
• Collaborate with RTL, DFT, tool owners and EDA vendors to improve methodologies and flows.
• Develop and implement timing ECOs and convergence strategies for multi-mode/multi-corner designs.
• Lead automation and scripting efforts to streamline STA tools and methodology development.
• Provide robust debugging and creative solutions for implementation issues.

Skills

Scripting TCL

Python

Perl

Shell

STA/Timing closure

Power integrity

Floor planning

Place & Route

Clock distribution

Education

Bachelor's or Master’s Degree in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys ICC2

Primetime-DMSA

Synopsys Formality

Cadence Calibre

Apache Redhawk

Synopsys ICV

Job description

Meet The Team

Our creative and talented Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation state-of-the- art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.

Your Impact

Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and "best known methods" to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST

Minimum Qualification

Bachelor's or a Master’s Degree in Electrical or Computer Engineering required. You are an ASIC engineer with 13+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies.

Preferred Qualifications

Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2

Synthesis Tools: Synopsys DC/FC

Formal Verification : Synopsys Formality and Cadence LEC

Static Timing verification: Primetime-DMSA

Power Integrity : Apache Redhawk

Physical Design Verification Synopsys ICV, Mentor Calibre

Scripting: TCL, Perl is required; Python is a plus

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Company Culture & Climate

Cisconians power the future. We make impact as a team, innovating fast and fearlessly to create meaningful solutions on a large scale. The depth and breadth of our technology doesn't just benefit our customers – it also means limitless opportunities for us to experiment and learn. We understand the power each of our unique backgrounds bring when we work together. Because of that, we have a global network of thinkers, doers, experts, and curious creators who help one another do their life’s best work.