ASIC Engineering Technical Leader || Physical Design | Floor Planning | GSP & PD | Exp - 11+ years

Cisco; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

Cisco in Bengaluru, India, seeks an experienced ASIC Physical Design engineer to shape next-generation networking chips in advanced process nodes. You will drive RTL-to-GDS flow, floor planning, place & route, timing closure, power integrity, and verification, collaborating with RTL, DFT, tool owners, and EDA vendors.

The role requires 13+ years of ASIC experience, large-design expertise, and strong scripting (TCL, Python, Perl).

Qualifications

• Bachelor's or Master’s in Electrical or Computer Engineering
• 13+ years of ASIC experience with broad tech including ASIC Physical implementation
• Experience with large designs (>100M gates) using sub 16/14/7/5/3nm nodes
• Familiarity with Design for Yield and Manufacturability, multi-Vt strategies

Responsibilities

• Analyze current generation quality and efficiency gaps to identify changes to Tools, Flow and Methodology.
• Collaborate with physical design, RTL, DFT, tool owners, and EDA vendors to improve methodologies.
• Provide feedback on CTS strategies to the Implementation Team.
• Drive methodologies and automation to streamline physical design work.
• Develop STA setup, convergence methodology, and sign-off for Multi-Mode and Multi-Corner designs.
• Develop Timing ECO flows and Tweaker/Primetime-based ECOs.
• Create and debug automation scripts for STA tools; propose creative solutions.
• Evaluate timing methodologies/tools across designs and nodes.

Skills

TCL scripting

Python

Perl

Shell scripting

Education

Bachelor's or Master’s in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys ICC2

Synopsys DC/FC

Primetime-DMSA

Cadence LEC

Primetime

Calibre ICV

Apache Redhawk

Job description

Meet The Team

Our creative and talented Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation state-of-the- arc networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.

Meet The Team

Our creative and talented Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation state-of-the- arc networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.

Your Impact

• Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
• Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
• Good understanding of different CTS strategies and providing the feedback to Implementation Team.
• As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work.
• STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
• Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
• Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Good scripting skills (TCL/SHELL/PERL/Python) is a MUST

Minimum Qualification

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
• You are an ASIC engineer with 13+ years of related work experience with a broad mix of technologies including:
• All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Hierarchical design implementation approach, Timing closure, physical convergence.
• Power Integrity Analysis
• Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
• Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies.

Preffered Qualifications

• Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2
• Synthesis Tools: Synopsys DC/FC
• Formal Verification : Synopsys Formality and Cadence LEC
• Static Timing verification: Primetime-DMSA
• Power Integrity : Apache Redhawk
• Physical Design Verification Synopsys ICV, Mentor Calibre
• Scripting: TCL, Perl is required; Python is a plus

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

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