ASIC Digital Engineer (SOC Validation) with 3 to 5 years of experience

SanDisk; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Sandisk is seeking a verification/validation engineer to understand ASIC specs and develop tests for pre-/post-silicon validation. You will own end-to-end verification flows, work with cross-functional teams, and sign off on deliverables. Proficiency in C, Python, SystemVerilog/UVM and experience with emulation platforms is desirable.

Responsibilities include debugging, testbench development, and creating regression suites to improve SoC coverage across DDR/PCIe/LPDDR protocols.

Qualifications

• BE or MS in Electrical Engineering or Computer Engineering with 4-6 years of SoC pre-/post-silicon verification and bring-up.
• Deep understanding of C, embedded programming, and hardware/software co-validation.
• Strong knowledge of SoC verification environments, SystemVerilog and UVM concepts.
• Proven track record of developing and executing verification and validation strategies for complex SoCs.

Responsibilities

• End-to-end ownership of one or more subsystems or SoC verification/validation flows including planning, execution, and closure.
• Experience with DDR, PCIe, LPDDR, USB, Ethernet, I2C, I3C, SPI, AXI, AHB and APB protocol verification.
• Run verification scenarios on emulation platforms to accelerate debug and improve pre-silicon coverage.
• Contribute to complex SoC‑level testbenches and UVM/ SystemVerilog components.
• Debug and perform initial root-cause analysis in simulation environments.
• Pre-/post-silicon bring-up including board init, power-on sequences, processor boot, and system-level debug.
• Validate datapath flows and port scenarios across pre-/post-silicon environments.
• Hands-on post-silicon ASIC bring-up, validation and debug.
• Develop firmware, bare-metal tests, and HAL code for datapath and SoC validation.
• Scripting in C, Python or Perl for test automation and data analysis.
• Build and maintain validation infrastructure and regression content.
• Debug across digital logic, firmware, timing, low-power, and DFT using JTAG and traces.
• Validate power and GLS patterns with UPF/CPF and gate-level simulations.
• Perform performance/stress testing and regression to improve SoC coverage.
• Apply constrained-random, coverage-driven and assertion-based verification methodologies.

Skills

C programming

Embedded systems

SystemVerilog

UVM

SoC verification

Python scripting

Test strategy

Education

BE or MS in Electrical/Computer Engineering

Tools

Palladium Emulation

Job description

Job Description

• Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre‑and post‑silicon validation.
• Independently developing and executing tests for verification and validation.
• Collaborating with cross‑functional teams to drive closure of verification and validation activities.
• Signing off on verification and validation deliverables.
• Debugging and root cause analysis of issues found during validation.
• Developing and maintaining automated test environments and regression suites.
• Contributing to continuous improvement of verification methodologies and best practices.

Your work will enable industry‑leading data storage control SoCs that are deployed in high‑volume consumer and enterprise products.

Qualifications

• BE or MS degree in Electrical Engineering or Computer Engineering, with 4-6 years of experience in SoC pre‑/post‑silicon verification, validation, and bring‑up.
• Deep understanding of C, embedded programming, and hardware/software co‑validation methodologies.
• Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts.
• Proven history of developing and executing verification and validation strategies for complex SoCs.

Essential Duties and Responsibilities

• Ownership of end‑to‑end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure.
• Protocol expertise: experience in verification and validation of industry‑standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB.
• Emulation experience: run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre‑silicon coverage.
• Testbench proficiency: must understand and contribute to complex SoC‑level testbenches, including UVM, C, and SystemVerilog components.
• Simulation and debug: execute verification and validation cases in simulation environments and perform initial debug and root cause analysis.
• Pre‑/post‑silicon validation: strong experience in bring‑up, including board initialization, power‑on sequences, processor boot, and system‑level debug for both pre‑ and post‑silicon phases.
• Datapath validation: ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environments, and port them across pre‑silicon and post‑silicon environments.
• Post‑silicon experience: hands‑on experience in post‑silicon ASIC bring‑up, validation, and debug.
• Firmware and HAL development: develop firmware, bare‑metal tests, and Hardware Abstraction Layer (HAL) code to enable datapath, integration, and SoC‑level validation and verification.
• Language proficiency: should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development.
• Validation infrastructure: build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes).
• Debug expertise: proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low‑power, DFT) using JTAG, trace, waveform capture, and performance counters.
• Power and GLS validation: run and debug gate‑level simulations, power‑aware (UPF/CPF) validation, and validate ATE functional patterns.
• Performance and stress testing: validate and verify performance bottlenecks, traffic generation, and corner‑case stress scenarios at the SoC level.
• Verification methodology: apply advanced verification methodologies, including constrained‑random, coverage‑driven, and assertion‑based verification to ensure design quality and completeness.

Additional Information

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

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