ASIC DFT Engineering Technical Leader Scan ATPG MBIST

Cisco; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Cisco's Common Hardware Group in Hyderabad seeks an ASIC Implementation Technical Lead focused on Design-for-Test. You will collaborate with Front-end RTL and backend PD teams to drive DFT requirements across the implementation flow and post-silicon validation.

You will own verification strategies, timing closure, and interface with vendors on full chip issues, contributing to next-generation networking chips and high-performance ASIC architectures.

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering required with 12+ years of experience.
• Experience with JTAG protocols (p1500, p1687), SCAN insertion and BIST architectures including memory BIST and boundary scan.
• Experience with ATPG and EDA tools and timing closure, including pattern translation and post-silicon validation.

Responsibilities

• Define and architect high-performance ASICs with strong DFT integration.
• Own verification strategies and collaborate with RTL and PD/DV teams.
• Drive design-for-test methodology from conception through production.

Skills

JTAG protocols

Scan insertion

BIST architectures

ATPG & timing closure

Gate-level simulation

Scripting: Tcl/Python/Perl

Pattern translation

VCS debugging

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

TestMax/Tetramax/Tessent

VCS

SDF timing analysis

Job description

Job Description:

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Key Contributions

• Manages the definition, architecture and design of high performance ASICs
• Owns applications or multiple complex functional areas
• Oversees reusable code and its applications
• Creates re-usable code that promotes efficiencies in new ways
• Defines verification strategies
• Coordinates with appropriate stakeholders to integrate into PD and DV flows
• Owns infrastructure and testing environmens
• Leads and designs the building blocks of multiple channels
• Applies and drives the design methodology from conception to production
• Influences and collaborates with teams to ensure specifications and requirements are met
• Leads technical expertise of a physical design function
• Interfaces with vendors and design leads on full chip timing closure, PI, and PV
• Owns the full electrical planning and specifications of electrical interfaces
• Develops multiple solutions, first test vehicles and performs verification and validation

Minimum Qualifications

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 12+ years of experience.
• Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan.
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure,
• Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.
• Scripting skills: Tcl, Python/Perl.

Preferred Qualifications

• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development - Test Architecture, Methodology and Infrastructure

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.