ASIC DFT Engineer || DFT/ATPG/MBIST/SCAN/JTAG || 8+ years

Cisco Systems, Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Cisco Systems, Inc. is seeking an experienced ASIC Design for Test Hardware Engineer in Bengaluru to drive DFT features for high-end silicon.

Lead development of DFT IP, collaborate with design, verification, and PD teams to ensure robust testability across RTL and post-silicon validation, and work with ATE patterns while mentoring peers. You will leverage expertise in JTAG, ATPG, and EDA tools, with scripting proficiency in Tcl/Python/Perl, and contribute to rapid diagnostics and robust design

Qualifications

• Bachelor’s or Master’s Degree in Electrical or Computer Engineering.
• Experience with DFT, test and silicon engineering trends.
• Experience with JTAG protocols, Scan insertion and ATPG.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.
• Knowledge of gate-level simulation and debugging with VCS.
• Post-silicon validation and debug experience; ATE pattern familiarity.
• Strong verbal communication skills and teamwork.
• Scripting skills: Tcl, Python/Perl.

Responsibilities

• Implement Hardware Design-for-Test features for ATE, in-system test, debug and diagnostics needs of the designs.
• Develop innovative DFT IP in collaboration with multi-functional teams and integrate testability features with RTL.
• Work with design/verification and PD teams to enable test logic integration across implementation and post-silicon validation flows.
• Craft solutions and debug with minimal mentorship.
• Provide 8-10 years of related ASIC DFT experience across diverse tech areas.

Skills

DFT concepts

JTAG protocols

ATPG

Scripting Tcl/Python/Perl

Verbal communication

Silicon engineering

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

TestMax

Tetramax

Tessent

VCS

Job description

Meet the Team

Join the Cisco Silicon One team and drive innovation at the heart of next-generation network devices—Cisco Silicon One™. Our unique team operates in a startup-like environment within a world-class corporation, pushing the boundaries of advanced silicon technologies. Our design center brings together all silicon hardware and software development disciplines, promoting an atmosphere of collaboration, technical leadership, and excellence.

We are transforming the networking industry and building the future of the internet for the 5G era. With Cisco Silicon One™, we deliver a unified, programmable silicon architecture—the foundation of all Cisco’s future routing products. Our platform offers high-speed networking, programmability, power efficiency, and scalability for service provider and web-scale markets.

Your Impact

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.

• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.

• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.

• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

• You are an ASIC Design for Test Hardware Engineer with 8-10 years of related work experience with a broad mix of technologies.

Minimum Qualifications:

• Bachelor’s or a Master’s Degree in Electrical or Computer Engineering required with at least 8-10 years of experience.

• Knowledge of the latest innovative trends in DFT, test and silicon engineering.

• Experience with Jtag protocols, Scan insertion and ATPG.

• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.

• Knowledge of the latest innovative trends in DFT, test and silicon engineering.

• Experience working with Gate level simulation, debugging with VCS and other simulators.

• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687

• Strong verbal skills and ability to thrive in a multifaceted environment

• Scripting skills: Tcl, Python/Perl.

Preferred Qualifications:

Test Static Timing Analysis

Post silicon validation using DFT patterns. raining: Completed all mandatory corporate trainings, including Fraudulent Applicants, Insider Threats, and BSCC guidelines, to ensure operational compliance.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era—and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.